Fix DmaConfig related flags and member order in structure
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@ -148,12 +148,12 @@ typedef enum {
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/// Configuration flags for \ref DmaConfig.
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enum {
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DMACFG_SRC_IS_DEVICE = BIT(0), ///< DMA source is a device/peripheral. Address will not auto-increment.
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DMACFG_DST_IS_DEVICE = BIT(1), ///< DMA destination is a device/peripheral. Address will not auto-increment.
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DMACFG_DST_IS_DEVICE = BIT(0), ///< DMA destination is a device/peripheral. Address will not auto-increment.
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DMACFG_SRC_IS_DEVICE = BIT(1), ///< DMA source is a device/peripheral. Address will not auto-increment.
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DMACFG_WAIT_AVAILABLE = BIT(2), ///< Make \ref svcStartInterProcessDma wait for the channel to be unlocked.
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DMACFG_KEEP_LOCKED = BIT(3), ///< Keep the channel locked after the transfer. Required for \ref svcRestartDma.
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DMACFG_USE_SRC_CONFIG = BIT(6), ///< Use the provided source device configuration even if the DMA source is not a device.
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DMACFG_USE_DST_CONFIG = BIT(7), ///< Use the provided destination device configuration even if the DMA destination is not a device.
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DMACFG_USE_DST_CONFIG = BIT(6), ///< Use the provided destination device configuration even if the DMA destination is not a device.
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DMACFG_USE_SRC_CONFIG = BIT(7), ///< Use the provided source device configuration even if the DMA source is not a device.
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};
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/// Configuration flags for \ref svcRestartDma.
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@ -185,8 +185,8 @@ typedef struct {
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s8 endianSwapSize; ///< Endian swap size (can be 0).
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u8 flags; ///< DMACFG_* flags.
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u8 _padding;
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DmaDeviceConfig dstCfg; ///< Destination device configuration, read if \ref DMACFG_DST_IS_DEVICE and/or \ref DMACFG_USE_DST_CONFIG are set.
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DmaDeviceConfig srcCfg; ///< Source device configuration, read if \ref DMACFG_SRC_IS_DEVICE and/or \ref DMACFG_USE_SRC_CONFIG are set.
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DmaDeviceConfig dstCfg; ///< Destination device configuration, read if \ref DMACFG_SRC_IS_DEVICE and/or \ref DMACFG_USE_SRC_CONFIG are set.
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} DmaConfig;
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///@}
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