GPU : command buffer stuff

This commit is contained in:
smea 2014-03-02 16:55:05 +01:00
parent 29baa1f757
commit 69613a3914
5 changed files with 39 additions and 39 deletions

View File

@ -79,40 +79,8 @@ void swapBuffers()
GSPGPU_WriteHWRegs(NULL, 0x400478, &regData, 4); GSPGPU_WriteHWRegs(NULL, 0x400478, &regData, 4);
} }
void copyBuffer() u32 gpuCmd[0x100];
{ u32 gpuCmdSize=0x100;
//copy topleft FB
u8 copiedBuffer=currentBuffer^1;
u8* bufAdr=&gspHeap[0x46500*copiedBuffer];
GSPGPU_FlushDataCache(NULL, bufAdr, 0x46500);
GX_RequestDma(gxCmdBuf, (u32*)bufAdr, (u32*)topLeftFramebuffers[copiedBuffer], 0x46500);
}
s32 pcCos(u16 v)
{
return costable[v&0x1FF];
}
u32 cnt;
void renderEffect()
{
u8* bufAdr=&gspHeap[0x46500*currentBuffer];
int i, j;
for(i=1;i<400;i++)
{
for(j=1;j<240;j++)
{
u32 v=(j+i*240)*3;
bufAdr[v]=(pcCos(i+cnt)+4096)/32;
bufAdr[v+1]=(pcCos(j-256+cnt)+4096)/64;
bufAdr[v+2]=(pcCos(i+128-cnt)+4096)/32;
}
}
cnt++;
}
int main() int main()
{ {
@ -134,13 +102,14 @@ int main()
if(status==APP_RUNNING) if(status==APP_RUNNING)
{ {
u32 PAD=hidSharedMem[7]; u32 PAD=hidSharedMem[7];
GPU_SetCommandBuffer(gpuCmd, gpuCmdSize, 0);
u32 regData=PAD|0x01000000; u32 regData=PAD|0x01000000;
GSPGPU_WriteHWRegs(NULL, 0x202A04, &regData, 4); GSPGPU_WriteHWRegs(NULL, 0x202A04, &regData, 4);
renderEffect(); GPU_RunCommandBuffer(gxCmdBuf);
swapBuffers(); swapBuffers();
copyBuffer();
} }
svc_sleepThread(16666666); svc_sleepThread(16666666);
} }

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@ -2,5 +2,8 @@
#define GPU_H #define GPU_H
void GPU_Init(Handle *gsphandle); void GPU_Init(Handle *gsphandle);
void GPU_SetCommandBuffer(u32* adr, u32 size, u32 offset);
void GPU_RunCommandBuffer(u32* gxbuf);
void GPU_AddCommand(u32* cmd, u32 length);
#endif #endif

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@ -7,7 +7,7 @@
#include <ctr/GSP.h> #include <ctr/GSP.h>
#include <ctr/svc.h> #include <ctr/svc.h>
#define APT_HANDLER_STACKSIZE (0x10000) #define APT_HANDLER_STACKSIZE (0x1000)
NS_APPID currentAppId; NS_APPID currentAppId;

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@ -43,6 +43,10 @@ const u32 gpuRegTopScreenInitTable[]={0x1EF00400, 0x000001C2,
0x1EF00498, 0x18300000, 0x1EF00498, 0x18300000,
0x1EF00478, 0x18300000}; 0x1EF00478, 0x18300000};
u32* gpuCmdBuf;
u32 gpuCmdBufSize;
u32 gpuCmdBufOffset;
Result writeRegisterValues(Handle* handle, u32* table, u32 num) Result writeRegisterValues(Handle* handle, u32* table, u32 num)
{ {
if(!table || !num)return -1; if(!table || !num)return -1;
@ -87,4 +91,28 @@ void GPU_Init(Handle *gsphandle)
data=0x10501; data=0x10501;
GSPGPU_WriteHWRegs(gsphandle, GSP_REBASE_REG(0x1EF00474), &data, 4); GSPGPU_WriteHWRegs(gsphandle, GSP_REBASE_REG(0x1EF00474), &data, 4);
gpuCmdBuf=NULL;
gpuCmdBufSize=0;
gpuCmdBufOffset=0;
}
void GPU_SetCommandBuffer(u32* adr, u32 size, u32 offset)
{
gpuCmdBuf=adr;
gpuCmdBufSize=size;
gpuCmdBufOffset=offset;
}
void GPU_RunCommandBuffer(u32* gxbuf)
{
GX_SetCommandList_Last(gxbuf, gpuCmdBuf, gpuCmdBufOffset*4, 0x3);
}
void GPU_AddCommand(u32* cmd, u32 length)
{
if(!cmd || !gpuCmdBuf || gpuCmdBufOffset+length>gpuCmdBufSize)return;
memcpy(&gpuCmdBuf[gpuCmdBufOffset], cmd, length*4);
gpuCmdBufOffset+=length;
} }

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@ -24,9 +24,9 @@ Result GX_SetCommandList_Last(u32* gxbuf, u32* buf0a, u32 buf0s, u8 flags)
gxCommand[0]=0x01; //CommandID gxCommand[0]=0x01; //CommandID
gxCommand[1]=(u32)buf0a; //buf0 address gxCommand[1]=(u32)buf0a; //buf0 address
gxCommand[2]=(u32)buf0s; //buf0 size gxCommand[2]=(u32)buf0s; //buf0 size
gxCommand[3]=flags&1; gxCommand[3]=flags&1; //written to GSP module state
gxCommand[4]=gxCommand[5]=gxCommand[6]=0x0; gxCommand[4]=gxCommand[5]=gxCommand[6]=0x0;
gxCommand[7]=(flags>>1)&1; gxCommand[7]=(flags>>1)&1; //when non-zero, call svcFlushProcessDataCache() with the specified buffer
return GSPGPU_submitGxCommand(gxbuf, gxCommand, NULL); return GSPGPU_submitGxCommand(gxbuf, gxCommand, NULL);
} }