SHDR : fixed DVLE_SendOutmap
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04c2c2760a
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@ -121,10 +121,14 @@ void DVLE_SendOutmap(DVLE_s* dvle)
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int i;
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int i;
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u8 numAttr=0;
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u8 numAttr=0;
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u8 maxAttr=0;
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u8 attrMask=0;
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//TODO : should probably preprocess this
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//TODO : should probably preprocess this
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for(i=0;i<dvle->outTableSize;i++)
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for(i=0;i<dvle->outTableSize;i++)
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{
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{
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u32* out=¶m[dvle->outTableData[i].regID];
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u32* out=¶m[dvle->outTableData[i].regID];
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if(*out==0x1F1F1F1F)numAttr++;
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//desc could include masking/swizzling info not currently taken into account
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//desc could include masking/swizzling info not currently taken into account
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//also TODO : map out other output register values
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//also TODO : map out other output register values
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@ -137,10 +141,15 @@ void DVLE_SendOutmap(DVLE_s* dvle)
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case RESULT_TEXCOORD2: *out=0x1F1F1716; break;
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case RESULT_TEXCOORD2: *out=0x1F1F1716; break;
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}
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}
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if(dvle->outTableData[i].regID+1>numAttr)numAttr=dvle->outTableData[i].regID+1;
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attrMask|=1<<dvle->outTableData[i].regID;
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if(dvle->outTableData[i].regID+1>maxAttr)maxAttr=dvle->outTableData[i].regID+1;
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}
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}
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GPUCMD_AddSingleParam(0x000F004F, numAttr);
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GPUCMD_AddSingleParam(0x000F0251, numAttr-1); //?
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GPUCMD_AddSingleParam(0x000F024A, numAttr-1); //?
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GPUCMD_AddSingleParam(0x000F02BD, attrMask); //?
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GPUCMD_AddSingleParam(0x0001025E, numAttr-1); //?
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GPUCMD_AddSingleParam(0x000F004F, numAttr); //?
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GPUCMD_Add(0x800F0050, param, 0x00000007);
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GPUCMD_Add(0x800F0050, param, 0x00000007);
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}
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}
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