From db11dd9bbcf429480b23b03d9659436cd8ba7013 Mon Sep 17 00:00:00 2001 From: smea Date: Thu, 18 Dec 2014 21:11:53 -0800 Subject: [PATCH] GPUCMD_AddMaskedWrite, GPUCMD_AddWrite, GPUCMD_AddMaskedWrites, GPUCMD_AddWrites, GPUCMD_AddMaskedIncrementalWrites, GPUCMD_AddIncrementalWrites --- libctru/include/3ds/gpu/gpu.h | 14 +++++++++++--- libctru/source/gpu/gpu.c | 11 +++-------- libctru/source/gpu/shdr.c | 34 +++++++++++++++++----------------- 3 files changed, 31 insertions(+), 28 deletions(-) diff --git a/libctru/include/3ds/gpu/gpu.h b/libctru/include/3ds/gpu/gpu.h index ac25969..dc590e0 100644 --- a/libctru/include/3ds/gpu/gpu.h +++ b/libctru/include/3ds/gpu/gpu.h @@ -7,7 +7,7 @@ void GPU_Init(Handle *gsphandle); void GPU_Reset(u32* gxbuf, u32* gpuBuf, u32 gpuBufSize); //GPUCMD -#define GPUCMD_HEADER(consec, mask, reg) (((consec)<<31)|(((mask)&0xF)<<16)|((reg)&0x3FF)) +#define GPUCMD_HEADER(incremental, mask, reg) (((incremental)<<31)|(((mask)&0xF)<<16)|((reg)&0x3FF)) void GPUCMD_SetBuffer(u32* adr, u32 size, u32 offset); void GPUCMD_SetBufferOffset(u32 offset); @@ -15,10 +15,18 @@ void GPUCMD_GetBuffer(u32** adr, u32* size, u32* offset); void GPUCMD_AddRawCommands(u32* cmd, u32 size); void GPUCMD_Run(u32* gxbuf); void GPUCMD_FlushAndRun(u32* gxbuf); -void GPUCMD_Add(u32 cmd, u32* param, u32 paramlength); -void GPUCMD_AddSingleParam(u32 cmd, u32 param); +void GPUCMD_Add(u32 header, u32* param, u32 paramlength); void GPUCMD_Finalize(); +#define GPUCMD_AddSingleParam(header, param) GPUCMD_Add((header), (u32[]){(u32)(param)}, 1) + +#define GPUCMD_AddMaskedWrite(reg, mask, val) GPUCMD_AddSingleParam(GPUCMD_HEADER(0, (mask), (reg)), (val)) +#define GPUCMD_AddWrite(reg, val) GPUCMD_AddMaskedWrite((reg), 0xF, (val)) +#define GPUCMD_AddMaskedWrites(reg, mask, vals, num) GPUCMD_Add(GPUCMD_HEADER(0, (mask), (reg)), (vals), (num)) +#define GPUCMD_AddWrites(reg, vals, num) GPUCMD_AddMaskedWrites((reg), 0xF, (vals), (num)) +#define GPUCMD_AddMaskedIncrementalWrites(reg, mask, vals, num) GPUCMD_Add(GPUCMD_HEADER(1, (mask), (reg)), (vals), (num)) +#define GPUCMD_AddIncrementalWrites(reg, vals, num) GPUCMD_AddMaskedIncrementalWrites((reg), 0xF, (vals), (num)) + //tex param #define GPU_TEXTURE_MAG_FILTER(v) (((v)&0x1)<<1) //takes a GPU_TEXTURE_FILTER_PARAM #define GPU_TEXTURE_MIN_FILTER(v) (((v)&0x1)<<2) //takes a GPU_TEXTURE_FILTER_PARAM diff --git a/libctru/source/gpu/gpu.c b/libctru/source/gpu/gpu.c index 6e0586d..303da75 100644 --- a/libctru/source/gpu/gpu.c +++ b/libctru/source/gpu/gpu.c @@ -60,7 +60,7 @@ void GPUCMD_FlushAndRun(u32* gxbuf) GX_SetCommandList_Last(gxbuf, gpuCmdBuf, gpuCmdBufOffset*4, 0x0); } -void GPUCMD_Add(u32 cmd, u32* param, u32 paramlength) +void GPUCMD_Add(u32 header, u32* param, u32 paramlength) { u32 zero=0x0; @@ -73,10 +73,10 @@ void GPUCMD_Add(u32 cmd, u32* param, u32 paramlength) if(!gpuCmdBuf || gpuCmdBufOffset+paramlength+1>gpuCmdBufSize)return; paramlength--; - cmd|=(paramlength&0x7ff)<<20; + header|=(paramlength&0x7ff)<<20; gpuCmdBuf[gpuCmdBufOffset]=param[0]; - gpuCmdBuf[gpuCmdBufOffset+1]=cmd; + gpuCmdBuf[gpuCmdBufOffset+1]=header; if(paramlength)memcpy(&gpuCmdBuf[gpuCmdBufOffset+2], ¶m[1], paramlength*4); @@ -85,11 +85,6 @@ void GPUCMD_Add(u32 cmd, u32* param, u32 paramlength) if(paramlength&1)gpuCmdBuf[gpuCmdBufOffset++]=0x00000000; //alignment } -void GPUCMD_AddSingleParam(u32 cmd, u32 param) -{ - GPUCMD_Add(cmd, ¶m, 1); -} - void GPUCMD_Finalize() { GPUCMD_AddSingleParam(0x0008025E, 0x00000000); diff --git a/libctru/source/gpu/shdr.c b/libctru/source/gpu/shdr.c index 0efe3fa..60952e8 100644 --- a/libctru/source/gpu/shdr.c +++ b/libctru/source/gpu/shdr.c @@ -77,12 +77,12 @@ void DVLP_SendCode(DVLP_s* dvlp, SHDR_type type) u32 regOffset=(type==GEOMETRY_SHDR)?(-0x30):(0x0); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_VSH_CODETRANSFER_CONFIG)+regOffset, 0x00000000); + GPUCMD_AddWrite(GPUREG_VSH_CODETRANSFER_CONFIG+regOffset, 0x00000000); int i; for(i=0;icodeSize;i+=0x80)GPUCMD_Add(GPUCMD_HEADER(0, 0xF, GPUREG_VSH_CODETRANSFER_DATA)+regOffset, &dvlp->codeData[i], ((dvlp->codeSize-i)<0x80)?(dvlp->codeSize-i):0x80); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_VSH_CODETRANSFER_END)+regOffset, 0x00000001); + GPUCMD_AddWrite(GPUREG_VSH_CODETRANSFER_END+regOffset, 0x00000001); } void DVLP_SendOpDesc(DVLP_s* dvlp, SHDR_type type) @@ -91,7 +91,7 @@ void DVLP_SendOpDesc(DVLP_s* dvlp, SHDR_type type) u32 regOffset=(type==GEOMETRY_SHDR)?(-0x30):(0x0); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_VSH_OPDESCS_CONFIG)+regOffset, 0x00000000); + GPUCMD_AddWrite(GPUREG_VSH_OPDESCS_CONFIG+regOffset, 0x00000000); u32 param[0x20]; @@ -137,12 +137,12 @@ void DVLE_SendOutmap(DVLE_s* dvle) if(dvle->outTableData[i].regID+1>maxAttr)maxAttr=dvle->outTableData[i].regID+1; } - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_0251), numAttr-1); //? - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_024A), numAttr-1); //? - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_VSH_OUTMAP_MASK)+regOffset, attrMask); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0x1, GPUREG_PRIMITIVE_CONFIG), numAttr-1); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_SH_OUTMAP_TOTAL), numAttr); - GPUCMD_Add(GPUCMD_HEADER(1, 0xF, GPUREG_SH_OUTMAP_O0), param, 0x00000007); + GPUCMD_AddWrite(GPUREG_0251, numAttr-1); //? + GPUCMD_AddWrite(GPUREG_024A, numAttr-1); //? + GPUCMD_AddWrite(GPUREG_VSH_OUTMAP_MASK+regOffset, attrMask); + GPUCMD_AddMaskedWrite(GPUREG_PRIMITIVE_CONFIG, 0x1, numAttr-1); + GPUCMD_AddWrite(GPUREG_SH_OUTMAP_TOTAL, numAttr); + GPUCMD_AddIncrementalWrites(GPUREG_SH_OUTMAP_O0, param, 0x00000007); } void DVLE_SendConstants(DVLE_s* dvle) @@ -169,7 +169,7 @@ void DVLE_SendConstants(DVLE_s* dvle) param[0x2]=rev[1]; param[0x3]=rev[0]; - GPUCMD_Add(GPUCMD_HEADER(1, 0xF, GPUREG_VSH_FLOATUNIFORM_CONFIG)+regOffset, param, 0x00000004); + GPUCMD_AddIncrementalWrites(GPUREG_VSH_FLOATUNIFORM_CONFIG+regOffset, param, 0x00000004); } } @@ -181,23 +181,23 @@ void SHDR_UseProgram(DVLB_s* dvlb, u8 id) u32 regOffset=(dvlb->DVLE[id].type==GEOMETRY_SHDR)?(-0x30):(0x0); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0x1, GPUREG_GEOSTAGE_CONFIG), 0x00000000); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0x1, GPUREG_0244), (dvlb->DVLE[id].type==GEOMETRY_SHDR)?0x1:0x0); + GPUCMD_AddMaskedWrite(GPUREG_GEOSTAGE_CONFIG, 0x1, 0x00000000); + GPUCMD_AddMaskedWrite(GPUREG_0244, 0x1, (dvlb->DVLE[id].type==GEOMETRY_SHDR)?0x1:0x0); DVLP_SendCode(&dvlb->DVLP, dvlb->DVLE[id].type); DVLP_SendOpDesc(&dvlb->DVLP, dvlb->DVLE[id].type); DVLE_SendConstants(dvle); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0x8, GPUREG_GEOSTAGE_CONFIG), 0x00000000); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_VSH_ENTRYPOINT)-regOffset, 0x7FFF0000|(dvle->mainOffset&0xFFFF)); //set entrypoint + GPUCMD_AddMaskedWrite(GPUREG_GEOSTAGE_CONFIG, 0x8, 0x00000000); + GPUCMD_AddWrite(GPUREG_VSH_ENTRYPOINT-regOffset, 0x7FFF0000|(dvle->mainOffset&0xFFFF)); //set entrypoint - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_0252), 0x00000000); // should all be part of DVLE_SendOutmap ? + GPUCMD_AddWrite(GPUREG_0252, 0x00000000); // should all be part of DVLE_SendOutmap ? DVLE_SendOutmap(dvle); //? - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_0064), 0x00000001); - GPUCMD_AddSingleParam(GPUCMD_HEADER(0, 0xF, GPUREG_006F), 0x00000703); + GPUCMD_AddWrite(GPUREG_0064, 0x00000001); + GPUCMD_AddWrite(GPUREG_006F, 0x00000703); } //TODO