Correct MAD instruction encoding yet again & other miscellaneous fixes
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bc051ca6c9
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@ -56,8 +56,6 @@ enum
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COND_LE,
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COND_GT,
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COND_GE,
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COND_UNK1,
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COND_UNK2,
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};
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//-----------------------------------------------------------------------------
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@ -481,10 +481,6 @@ static inline int ensure_valid_condop(int condop, const char* name)
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ARG_TO_REG(_reg, _name); \
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safe_call(ensure_valid_src_narrow(_reg, _name, 2))
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#define ARG_TO_SRC2_REG2(_reg, _name) \
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ARG_TO_REG2(_reg, _name); \
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safe_call(ensure_valid_src_narrow(_reg, _name, 1))
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#define ARG_TO_IREG(_reg, _name) \
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ARG_TO_REG(_reg, _name); \
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safe_call(ensure_valid_ireg(_reg, _name))
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@ -573,8 +569,6 @@ static inline int parseCondOp(const char* name)
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if (stricmp(name, "le")==0) return COND_LE;
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if (stricmp(name, "gt")==0) return COND_GT;
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if (stricmp(name, "ge")==0) return COND_GE;
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if (*name == '6') return COND_UNK1;
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if (*name == '7') return COND_UNK2;
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return -1;
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}
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@ -660,32 +654,32 @@ static int parseReg(char* pos, int& outReg, int& outSw, int* idxType = NULL)
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switch (*pos)
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{
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case 'o': // Output registers
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if (outReg < 0x00 || outReg >= 0x08)
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return throwError("invalid output register: %s(%d)\n", pos);
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if (outReg < 0x00 || outReg >= 0x07)
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return throwError("invalid output register: %s\n", pos);
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break;
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case 'v': // Input attributes
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if (outReg < 0x00 || outReg >= 0x0F)
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return throwError("invalid input register: %s(%d)\n", pos);
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return throwError("invalid input register: %s\n", pos);
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break;
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case 'r': // Temporary registers
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outReg += 0x10;
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if (outReg < 0x10 || outReg >= 0x20)
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return throwError("invalid temporary register: %s(%d)\n", pos);
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return throwError("invalid temporary register: %s\n", pos);
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break;
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case 'c': // Floating-point vector uniform registers
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outReg += 0x20;
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if (outReg < 0x20 || outReg >= 0x80)
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return throwError("invalid floating-point vector uniform register: %s(%d)\n", pos);
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return throwError("invalid floating-point vector uniform register: %s\n", pos);
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break;
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case 'i': // Integer vector uniforms
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outReg += 0x80;
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if (outReg < 0x80 || outReg >= 0x88)
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return throwError("invalid integer vector uniform register: %s(%d)\n", pos);
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return throwError("invalid integer vector uniform register: %s\n", pos);
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break;
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case 'b': // Boolean uniforms
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outReg += 0x88;
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if (outReg < 0x88 || outReg >= 0x98)
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return throwError("invalid boolean uniform register: %s(%d)\n", pos);
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return throwError("invalid boolean uniform register: %s\n", pos);
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break;
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}
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outReg += regOffset;
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@ -839,20 +833,22 @@ DEF_COMMAND(format5)
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ENSURE_NO_MORE_ARGS();
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ARG_TO_DEST_REG(rDest, destName);
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ARG_TO_SRC2_REG2(rSrc1, src1Name);
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ARG_TO_REG(rSrc2, src2Name);
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ARG_TO_REG(rSrc3, src3Name);
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ARG_TO_SRC2_REG(rSrc1, src1Name);
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ARG_TO_REG2(rSrc2, src2Name);
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ARG_TO_REG2(rSrc3, src3Name);
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bool inverted = opcodei >= 0 && rSrc2 < 0x20 && rSrc3 >= 0x20;
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bool inverted = opcodei >= 0 && rSrc2 < 0x20 && (rSrc3 >= 0x20 || (rSrc3Idx && !rSrc2Idx));
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if (!inverted)
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{
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safe_call(ensure_valid_src_wide(rSrc2, src2Name, 2));
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safe_call(ensure_valid_src_narrow(rSrc3, src3Name, 3));
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safe_call(ensure_no_idxreg(rSrc3Idx, 2));
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} else
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{
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safe_call(ensure_valid_src_narrow(rSrc2, src2Name, 2));
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safe_call(ensure_valid_src_wide(rSrc3, src3Name, 3));
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safe_call(ensure_no_idxreg(rSrc2Idx, 2));
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}
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int opdesc = 0;
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@ -865,9 +861,9 @@ DEF_COMMAND(format5)
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printf("%s:%02X d%02X, d%02X, d%02X, d%02X (0x%X)\n", cmdName, opcode, rDest, rSrc1, rSrc2, rSrc3, opdesc);
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#endif
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if (!inverted)
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BUF.push_back(FMT_OPCODE(opcode) | opdesc | (rSrc3<<5) | (rSrc2<<10) | (rSrc1<<17) | (rSrc1Idx<<22) | (rDest<<24));
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BUF.push_back(FMT_OPCODE(opcode) | opdesc | (rSrc3<<5) | (rSrc2<<10) | (rSrc1<<17) | (rSrc2Idx<<22) | (rDest<<24));
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else
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BUF.push_back(FMT_OPCODE(opcodei) | opdesc | (rSrc3<<5) | (rSrc2<<12) | (rSrc1<<17) | (rSrc1Idx<<22) | (rDest<<24));
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BUF.push_back(FMT_OPCODE(opcodei) | opdesc | (rSrc3<<5) | (rSrc2<<12) | (rSrc1<<17) | (rSrc3Idx<<22) | (rDest<<24));
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return 0;
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}
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@ -924,7 +920,7 @@ DEF_COMMAND(formatsetemit)
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NEXT_ARG_OPT(flagStr, NULL);
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ENSURE_NO_MORE_ARGS();
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ARG_TO_INT(vtxId, vtxIdStr, 0, 3);
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ARG_TO_INT(vtxId, vtxIdStr, 0, 2);
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bool isPrim, isInv;
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safe_call(parseSetEmitFlags(flagStr, isPrim, isInv));
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