From 77514941604212337976574531fa4398938d204d Mon Sep 17 00:00:00 2001 From: Cameron Gutman Date: Thu, 23 Apr 2026 21:18:05 -0500 Subject: [PATCH] atomic: Use DMB ISHLD for aarch64 acquire barrier This is a little more efficient than a DMB ISH and matches what GCC, Clang, and MSVC generate for a C++11 acquire fence. --- include/SDL_atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/SDL_atomic.h b/include/SDL_atomic.h index 064276fefd..970ec97dc7 100644 --- a/include/SDL_atomic.h +++ b/include/SDL_atomic.h @@ -182,7 +182,7 @@ extern DECLSPEC void SDLCALL SDL_MemoryBarrierAcquireFunction(void); #define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("lwsync" : : : "memory") #elif defined(__GNUC__) && defined(__aarch64__) #define SDL_MemoryBarrierRelease() __asm__ __volatile__ ("dmb ish" : : : "memory") -#define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("dmb ish" : : : "memory") +#define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("dmb ishld" : : : "memory") #elif defined(__GNUC__) && defined(__arm__) #if 0 /* defined(__LINUX__) || defined(__ANDROID__) */ /* Information from: