From f2206974b098d2fbd61fdaf1a01513b6831b60d9 Mon Sep 17 00:00:00 2001 From: Cameron Gutman Date: Thu, 23 Apr 2026 20:57:35 -0500 Subject: [PATCH] atomic: Use DMB ISHLD for aarch64 acquire barrier This is a little more efficient than a DMB ISH and matches what GCC, Clang, and MSVC generate for a C++11 acquire fence. --- include/SDL3/SDL_atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/SDL3/SDL_atomic.h b/include/SDL3/SDL_atomic.h index bbd5828df3..91de812828 100644 --- a/include/SDL3/SDL_atomic.h +++ b/include/SDL3/SDL_atomic.h @@ -283,7 +283,7 @@ extern SDL_DECLSPEC void SDLCALL SDL_MemoryBarrierAcquireFunction(void); #define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("lwsync" : : : "memory") #elif defined(__GNUC__) && defined(__aarch64__) #define SDL_MemoryBarrierRelease() __asm__ __volatile__ ("dmb ish" : : : "memory") -#define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("dmb ish" : : : "memory") +#define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("dmb ishld" : : : "memory") #elif defined(__GNUC__) && defined(__arm__) #if 0 /* defined(SDL_PLATFORM_LINUX) || defined(SDL_PLATFORM_ANDROID) */ /* Information from: