backend: Do not use random generator for reg allocation (#7)

CMakeLists.txt

@@ -145,7 +145,7 @@ set(TSL_ROBIN_MAP_ENABLE_INSTALL ON)
 
 find_package(Boost 1.57 REQUIRED)
 find_package(fmt 9 CONFIG)
-find_package(mcl 0.1.12 EXACT CONFIG)
+find_package(mcl 0.1.14 EXACT CONFIG)
 find_package(tsl-robin-map CONFIG)
 
 if ("arm64" IN_LIST ARCHITECTURE OR DYNARMIC_TESTS)

src/dynarmic/backend/arm64/reg_alloc.cpp

@@ -436,9 +436,10 @@ int RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
     std::vector<int> candidates;
     std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](int i) { return regs[i].MaybeAllocatable(); });
 
-    // TODO: LRU
-    std::uniform_int_distribution<size_t> dis{0, candidates.size() - 1};
-    return candidates[dis(rand_gen)];
+    // TODO: The candidate was chosen randomly before, and a LRU was
+    // suggested as an improvement. However, using an incrementing index
+    // seems to be close enough. Determine if an LRU is still needed.
+    return candidates[alloc_candidate_index++ % candidates.size()];
 }
 
 void RegAlloc::SpillGpr(int index) {

src/dynarmic/backend/arm64/reg_alloc.h

@@ -158,7 +158,7 @@ public:
     using ArgumentInfo = std::array<Argument, IR::max_arg_count>;
 
     explicit RegAlloc(oaknut::CodeGenerator& code, FpsrManager& fpsr_manager, std::vector<int> gpr_order, std::vector<int> fpr_order)
-            : code{code}, fpsr_manager{fpsr_manager}, gpr_order{gpr_order}, fpr_order{fpr_order}, rand_gen{std::random_device{}()} {}
+            : code{code}, fpsr_manager{fpsr_manager}, gpr_order{gpr_order}, fpr_order{fpr_order} {}
 
     ArgumentInfo GetArgumentInfo(IR::Inst* inst);
     bool WasValueDefined(IR::Inst* inst) const;
@@ -333,7 +333,7 @@ private:
     HostLocInfo flags;
     std::array<HostLocInfo, SpillCount> spills;
 
-    mutable std::mt19937 rand_gen;
+    mutable size_t alloc_candidate_index{};
 
     tsl::robin_set<const IR::Inst*> defined_insts;
 };

src/dynarmic/backend/riscv64/reg_alloc.cpp

@@ -269,9 +269,10 @@ u32 RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
     std::vector<u32> candidates;
     std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](u32 i) { return !regs[i].locked; });
 
-    // TODO: LRU
-    std::uniform_int_distribution<size_t> dis{0, candidates.size() - 1};
-    return candidates[dis(rand_gen)];
+    // TODO: The candidate was chosen randomly before, and a LRU was
+    // suggested as an improvement. However, using an incrementing index
+    // seems to be close enough. Determine if an LRU is still needed.
+    return candidates[alloc_candidate_index++ % candidates.size()];
 }
 
 void RegAlloc::SpillGpr(u32 index) {

src/dynarmic/backend/riscv64/reg_alloc.h

@@ -159,7 +159,7 @@ private:
     std::array<HostLocInfo, 32> fprs;
     std::array<HostLocInfo, SpillCount> spills;
 
-    mutable std::mt19937 rand_gen;
+    mutable size_t alloc_candidate_index{};
 };
 
 template<typename T>