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• 551e207661 A32: Implement ASIMD VSUB (integer) Lioncash 2020-06-18 22:18:54 -04:00
• 4d6f68525d A32: Implement ASIMD VADD (integer) Lioncash 2020-06-18 22:16:44 -04:00
• fbdae61c13 A32: Implement ASIMD VMVN (register) Lioncash 2020-06-18 21:58:17 -04:00
• b759773b3b a32_emit_x64: EmitVAddrLookup: Use 64-bit registers where required MerryMage 2020-06-19 00:44:37 +01:00
• 687c604197 Merge pull request #532 from lioncash/shift merry 2020-06-19 00:22:18 +01:00
• 7dd9901de2 a32_emit_x64: Incorrect type in ExclusiveWriteMemory MerryMage 2020-06-19 00:19:46 +01:00
• 00b2f9b319 asimd: Prevent misdecodes from occurring Lioncash 2020-06-18 14:59:32 -04:00
• 87f6e412d0 emit_x64_vector: SSE4.1 implementation of EmitVectorPolynomialMultiply{Long}8 MerryMage 2020-06-18 18:35:21 +01:00
• f5b41aabc6 emit_x64_vector: Implement EmitVectorPolynomialMultiplyLong64 in terms of pclmulqdq MerryMage 2020-06-18 18:04:23 +01:00
• 7402d38675 test_arm_instructions: Add vclt.f32 (zero) test MerryMage 2020-06-18 17:39:56 +01:00
• d34763242c Revert "A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero" MerryMage 2020-06-18 17:38:40 +01:00
• 179951b10f A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero Lioncash 2020-06-18 09:00:26 -04:00
• 6ca20c2fe3 A32: Implement ASIMD VSLI Lioncash 2020-06-18 11:32:06 -04:00
• 887732d8a8 A32: Implement ASIMD VSRI Lioncash 2020-06-18 11:28:12 -04:00
• 8b98c91ecc A32: Implement ASIMD VSHL Lioncash 2020-06-18 11:12:17 -04:00
• 69c999bc66 A32: Implement ASIMD VRSRA Lioncash 2020-06-18 11:03:29 -04:00
• 14fdd15199 A32: Implement ASIMD VRSHR Lioncash 2020-06-18 11:00:13 -04:00
• 276e0b71dc A32: Implement ASIMD VSRA Lioncash 2020-06-18 10:53:19 -04:00
• 054dff7cd5 A32: Implement ASIMD VTST Lioncash 2020-06-18 09:30:19 -04:00
• 6c142bc5cc A32: Implement ASIMD VSHR Lioncash 2020-06-18 09:34:31 -04:00
• 13367a7efd A64: Match A32 page_table code MerryMage 2020-06-18 11:27:12 +01:00
• 08350d06f1 A32: Implement ASIMD VQNEG Lioncash 2020-06-17 16:05:25 -04:00
• f6b665f5a4 A32: Implement ASIMD VQABS Lioncash 2020-06-17 15:53:35 -04:00
• b88c291f81 A32: Detect misaligned memory accesses MerryMage 2020-06-17 17:51:37 +01:00
• 9f3277540a Merge A32 and A64 exclusive monitors MerryMage 2020-06-17 10:28:24 +01:00
• 4b371c0445 A32: Implement ASIMD VREV{16, 32, 64} Lioncash 2020-06-16 13:12:36 -04:00
• 6dd2c94095 A32: Implement ASIMD VABS Lioncash 2020-06-16 12:05:39 -04:00
• 53422bec46 a64_emit_x64: Reduce code duplication in exclusive memory code MerryMage 2020-06-16 18:09:12 +01:00
• a1c9bb94a8 A32: Add yuzu-specific hacks MerryMage 2020-06-16 16:38:43 +01:00
• 2c1a4843ad A32 global exlcusive monitor MerryMage 2020-06-16 15:46:47 +01:00
• 58abdcce5b backend/x64/a32_*: Rename config to conf MerryMage 2020-06-16 13:36:09 +01:00
• 7ea521b8bf a32_emit_x64: Change ExclusiveWriteMemory64 to require a single U64 argument MerryMage 2020-06-16 13:32:50 +01:00
• aa341b7eea a32_emit_x64: Make ExclusiveWrite a member function of A32EmitX64 MerryMage 2020-06-16 12:58:18 +01:00
• 62e04845b1 A64/config: Provide default implementation of MemoryWriteExclusive functions MerryMage 2020-06-16 11:52:51 +01:00
• 34ef5142e3 a32_emit_x64: Specify callback as template argument MerryMage 2020-06-16 10:20:37 +01:00
• 58b2c83944 a32_emit_x64: Reduce mov code duplication in {Read,Write}Memory MerryMage 2020-06-16 10:13:08 +01:00
• aabd0d824d A32: Add immediate creation helper Lioncash 2020-06-15 22:23:25 -04:00
• 93ed3441b7 A32: Implement ASIMD VCLS/VCLZ/VCNT Lioncash 2020-06-15 22:17:33 -04:00
• 9b06a938a9 fuzz_arm: Ignore endian bit Lioncash 2020-06-15 18:43:44 -04:00
• 15b3de95e4 A32: Implement VNEG Lioncash 2020-06-15 18:25:52 -04:00
• 2796a85096 interface/a32: Remove descriptor argument from Disassemble MerryMage 2020-06-12 15:27:42 +01:00
• 3ccc415c52 emit_x64_saturation: Improve codegen for saturated result in EmitSignedSaturation MerryMage 2020-06-12 15:24:37 +01:00
• e953f67201 emit_x64_packed: PackedAbsDiffSumS8: Fix case when bits above the lower 32 bits are not zero MerryMage 2020-06-12 15:24:09 +01:00
• 6cf5c78bfa Remove .gitmodules MerryMage 2020-06-11 15:15:05 +01:00
• 09867081dc gitignore: Add build-*/ MerryMage 2020-06-11 15:13:38 +01:00
• c4cf0b3e47 exception_handler_posix: Just disable fastmem if initialization fails MerryMage 2020-06-10 22:30:02 +01:00
• 55bddc767f backend/x64: Touch PEXT/PDEP code MerryMage 2020-06-09 22:28:28 +01:00
• f495018f53 block_of_code: Encapsulate CPU feature detection code MerryMage 2020-06-09 21:25:57 +01:00
• feddf69cb4 emit_x64_crc32: Use same constants MerryMage 2020-06-06 20:46:09 +01:00
• 66a356e6cb emit_x64_crc32: Further improvements to codegen MerryMage 2020-06-06 17:07:03 +01:00
• bb203429c6 crc32: Remove unnecessary masking MerryMage 2020-06-04 20:33:46 +01:00
• bcde135c23 emit_x64_crc32: Improve 64-bit PCLMULQDQ implementation of EmitCRC32ISO MerryMage 2020-06-04 19:06:25 +01:00
• 0f9c70ff42 emit_x64_crc32: Improve PCLMULQDQ implementation of EmitCRC32ISO MerryMage 2020-06-03 18:55:58 +01:00
• fa6aee434e emit_x64_crc32: PCLMULQDQ implementation of EmitCRC32ISO MerryMage 2020-06-03 11:16:53 +01:00
• b47adaee1d emit_x64_vector: SSSE3 implementation of EmitVectorExtract MerryMage 2020-06-01 15:41:29 +01:00
• f3845cea9a A32: Implement ASIMD VQSUB instruction MerryMage 2020-05-30 16:10:51 +01:00
• 16ff880f8f A32: Implement ASIMD VQADD MerryMage 2020-05-30 16:09:37 +01:00
• 174fbb74c5 simd_three_same: Use VectorSaturated{Signed,Unsigned}{Add,Sub} in SaturatingArithmeticOperation MerryMage 2020-05-30 15:22:53 +01:00
• 4e90754873 IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub} MerryMage 2020-05-30 15:21:55 +01:00
• 3a50d444dc A32: Implement ASIMD VHSUB MerryMage 2020-05-28 21:53:50 +01:00
• 205e6c5a56 A32: Implement ASIMD VRHADD MerryMage 2020-05-28 21:51:49 +01:00
• 946eb03a3b A32: Implement ASIMD VHADD MerryMage 2020-05-28 21:46:44 +01:00
• f8062345bb asimd_two_regs_misc: Use {Get,Set}Vector MerryMage 2020-05-28 21:05:30 +01:00
• 11cec1e3b6 asimd_three_same: Use {Get,Set}Vector MerryMage 2020-05-28 21:05:16 +01:00
• 7d0b16de32 asimd_one_reg_modified_immediate: Use {Get,Set}Vector MerryMage 2020-05-28 20:40:26 +01:00
• cae857b8c8 verification_pass: Have an appropriate assertion message MerryMage 2020-05-28 20:40:11 +01:00
• ebddf6cca0 basic_block: Allow printing of invalid instruction pointers MerryMage 2020-05-28 20:39:50 +01:00
• 07108246cf A32/IR: Add SetVector and GetVector MerryMage 2020-05-28 20:39:19 +01:00
• e85a08ec34 CMakeLists: MSVC: Weaken warning level for externals MerryMage 2020-05-21 22:31:54 +01:00
• 93c289b54f Use tsl::robin_map and tsl::robin_set MerryMage 2020-05-21 21:31:18 +01:00
• 91578edc69 externals: Add robin-map MerryMage 2020-05-26 20:51:11 +01:00
• 8bf66a678a Squashed 'externals/robin-map/' content from commit 5cf53c6f5 MerryMage 2020-05-26 20:51:11 +01:00
• c4a4bdd7de frontend: Relocate ExtReg handling to types.h Lioncash 2020-05-22 19:09:37 -04:00
• 1900df5340 frontend: Relocate advanced SIMD expansion to a common file Lioncash 2020-05-22 19:00:56 -04:00
• fc112e61f2 A32: Implement ASIMD modified immediate functions Lioncash 2020-05-22 18:04:34 -04:00
• 659d78c9c4 A32: Implement ASIMD VSWP Lioncash 2020-05-21 18:36:47 -04:00
• d0d50c4824 print_info: Use VFP and ASIMD decoders to get dynarmic name for instruction MerryMage 2020-05-17 22:40:20 +01:00
• d0075f4ea6 print_info: Use LLVM to disassemble A32 MerryMage 2020-05-17 22:30:46 +01:00
• c59a127e86 opcodes: Switch from std::map to std::array MerryMage 2020-05-17 17:00:18 +01:00
• d0b45f6150 A32: Implement ARMv8 VST{1-4} (multiple) MerryMage 2020-05-17 16:59:56 +01:00
• eb332b3836 asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction Lioncash 2020-05-16 13:36:02 -04:00
• f42b3ad4a0 A32: Implement ASIMD VBIF (register) Lioncash 2020-05-16 13:30:13 -04:00
• ee9a81dcba A32: Implement ASIMD VBIT (register) Lioncash 2020-05-16 13:27:39 -04:00
• d624059ead A32: Implement ASIMD VBSL (register) Lioncash 2020-05-16 13:24:18 -04:00
• 66663cf8e7 asimd_three_same: Collapse all bitwise implementations into a single code path Lioncash 2020-05-16 13:17:42 -04:00
• 4b5e3437cf A32: Implement ASIMD VEOR (register) Lioncash 2020-05-16 13:03:40 -04:00
• 67b284f6fa A32: Implement ASIMD VORN (register) Lioncash 2020-05-16 13:00:32 -04:00
• 1fdd90ca2a A32: Implement ASIMD VORR (register) Lioncash 2020-05-16 12:57:43 -04:00
• 9b93a9de46 a32_jitstate: Remove obsoleted debug assert Lioncash 2020-05-16 12:55:02 -04:00
• 64fa804dd4 A32: Implement ASIMD VBIC (register) Lioncash 2020-05-16 12:40:12 -04:00
• 0441ab81a1 A32: Implement ASIMD VAND (register) Lioncash 2020-05-16 11:31:17 -04:00
• 1b25e867ae asimd_load_store_structures: Simplify ToExtRegD() Lioncash 2020-05-16 11:26:02 -04:00
• 2169653c50 a64_emit_x64: Invalid regalloc code for EmitA64ExclusiveReadMemory128 MerryMage 2020-05-16 12:31:12 +01:00
• 1a0bc5ba91 A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple) MerryMage 2020-05-16 12:30:09 +01:00
• e7f1a0d408 A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H} MerryMage 2020-05-15 21:07:07 +01:00
• 8808b8c479 cpu_info: Make test non-allocating Lioncash 2020-05-10 21:20:21 -04:00
• af3b65b135 decoder_detail: Mark GetMaskAndExpect() as constexpr Lioncash 2020-05-10 20:45:56 -04:00
• 59db2c191a VFPv3: Implement VMOV (immediate) MerryMage 2020-05-10 15:09:37 +01:00
• 7f77a04900 fuzz_arm: Do not test vfp_VMRS MerryMage 2020-05-10 14:47:21 +01:00
• 3c86d58064 VFPv4: Implement VCVTB, VCVTT MerryMage 2020-05-10 14:45:18 +01:00