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  • 8bfaa9aac0 Merge pull request #407 from lioncash/div Merry 2018-10-11 15:50:47 +01:00
  • 8248999c5d constant_propagation_pass: Fold division operations where applicable Lioncash 2018-10-09 15:18:09 -04:00
  • d83eae2004 Merge pull request #406 from lioncash/mul Merry 2018-10-09 15:11:36 +01:00
  • 73d9393300 Merge pull request #405 from lioncash/inst Merry 2018-10-08 08:35:04 +01:00
  • 7ad6981437 constant_propagation_pass: deduplicate common 32/64 bit checking for results in folding functions Lioncash 2018-10-07 22:11:47 -04:00
  • f1a66c37ba a64: Add ARMv8.4+ instructions encodings to the encoding table Lioncash 2018-10-05 23:12:47 -04:00
  • 72daf37208 constant_propagation_pass: Fold Mul32 and Mul64 cases where applicable Lioncash 2018-10-07 21:48:42 -04:00
  • 546cfbc0ee Merge pull request #404 from lioncash/fold Merry 2018-10-07 16:40:11 +01:00
  • 43b2eb4688 constant_propagation_pass: Fold SignExtend{Type}ToLong opcodes if possible Lioncash 2018-10-05 18:14:56 -04:00
  • 2da2cf9058 constant_propagation_pass: Fold SignExtend{Type}ToWord opcodes if possible Lioncash 2018-10-05 18:08:16 -04:00
  • c42f6ea184 constant_propagation_pass: Fold ZeroExtend{Type}ToLong opcodes if possible Lioncash 2018-10-05 18:00:15 -04:00
  • 2274214ff0 constant_propagation_pass: Combine zero-extension folding code into its own function Lioncash 2018-10-05 17:45:33 -04:00
  • 4c6a9535ca Merge pull request #403 from lioncash/zero Merry 2018-10-04 17:57:11 +01:00
  • 0583d401e3 ir/value: Add IsSignedImmediate() and IsUnsignedImmediate() functions to Value's interface Lioncash 2018-10-04 05:18:22 -04:00
  • e3258e8525 ir/value: Add a GetImmediateAsS64() function Lioncash 2018-10-04 05:10:08 -04:00
  • 4a3c064b15 ir/value: Add an IsZero() member function to Value's interface Lioncash 2018-10-04 04:52:44 -04:00
  • 783fc707fa externals: Update fmt to 5.2.1 MerryMage 2020-04-22 20:57:22 +01:00
  • 5f7df9a182 Squashed 'externals/fmt/' changes from 135ab5cf..3e75ad98 MerryMage 2020-04-22 20:57:22 +01:00
  • c649f11c0a Merge pull request #401 from lioncash/folding Merry 2018-10-02 21:22:58 +01:00
  • 2524d536b0 A32/ir_emitter: Bugfix: ExceptionRaised was producing incorrect PC MerryMage 2018-09-30 19:39:11 +01:00
  • c09f4cf28e constant_propagation_pass: Fold NOT operations Lioncash 2018-09-29 04:07:32 -04:00
  • 8013548bbb constant_propagation_pass: Fold OR operations Lioncash 2018-09-29 03:57:16 -04:00
  • 898d096e39 constant_propagation_pass: Fold AND operations Lioncash 2018-09-29 03:24:35 -04:00
  • f40fcda1f6 ir/value: Add member function to check whether or not all bits of a contained value are set Lioncash 2018-10-01 18:35:31 -04:00
  • 0ea99b7d59 constant_propagation_pass: Fold EOR operations Lioncash 2018-09-28 17:42:34 -04:00
  • d69fceec55 value: Move ImmediateToU64() to be a part of Value's interface Lioncash 2018-09-28 14:46:38 -04:00
  • ca603c1215 reg_alloc: Emit AVX instructions where able MerryMage 2018-09-28 21:12:48 +01:00
  • e2358af5ef abi: Emit AVX instructions where able MerryMage 2018-09-28 21:12:17 +01:00
  • 7c0378f56d a64_exclusive_monitor: Loosen memory ordering requirements MerryMage 2018-09-27 16:21:56 +01:00
  • 6e3e251031 travis: Make macOS builds use Xcode 10 Lioncash 2018-09-24 20:33:03 -04:00
  • f0920c0ded Fix VShift terminology MerryMage 2018-09-23 10:50:39 +01:00
  • b51dae790d emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS16 MerryMage 2018-09-23 10:41:41 +01:00
  • bd47f2ca8f emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS64 MerryMage 2018-09-23 10:41:30 +01:00
  • 3bf183d7e8 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftS32 MerryMage 2018-09-23 10:21:49 +01:00
  • 94f9d402eb emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftU16() MerryMage 2018-09-23 10:14:10 +01:00
  • 6d9639e3b0 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU64() MerryMage 2018-09-23 10:04:23 +01:00
  • bbc066a266 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU32() MerryMage 2018-09-23 10:01:59 +01:00
  • da2e7fad87 emit_x64_vector: SSSE3 variant of EmitVectorCountLeadingZeros8() Lioncash 2018-09-23 00:44:45 -04:00
  • 9130ed45b9 Merge pull request #397 from VelocityRa/dec-shift-fix Mat M 2018-09-22 19:17:36 -04:00
  • c30b8dbe99 decoders: Cast to correctly-sized type before shifting VelocityRa 2018-09-22 21:00:50 +03:00
  • 238f2f2cd0 a64_emit_x64: Lowercase PAGE_SIZE MerryMage 2018-09-22 18:54:49 +01:00
  • 7162f6f254 emit_x64_vector_floating_point: SSE4.1 implementation of EmitFPVectorToFixed MerryMage 2018-09-22 17:25:19 +01:00
  • e7a5592699 emit_x64_vector_floating_point: EmitFPVectorRoundInt: Use FCODE MerryMage 2018-09-22 16:19:54 +01:00
  • b8fde48732 emit_x64_vector: AVX implementation for EmitVectorCountLeadingZeros8 MerryMage 2018-09-22 16:08:23 +01:00
  • fd37b637aa emit_x64_vector: SSE implementation of EmitVectorCountLeadingZeros16 MerryMage 2018-09-22 13:04:44 +01:00
  • 09bf273bc8 A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant MerryMage 2018-09-19 20:09:59 +01:00
  • 03ad2072a7 emit_x64_floating_point: Reduce fallback LUT code in EmitFPToFixed MerryMage 2018-09-19 19:50:42 +01:00
  • f9129db6fd A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant MerryMage 2018-09-19 19:47:28 +01:00
  • 48df9b9a7d A64: Implement UQSHL's vector immediate and register variants Lioncash 2018-09-18 18:55:15 -04:00
  • d426dfe942 ir: Add opcodes for unsigned saturating left shifts Lioncash 2018-09-18 18:09:47 -04:00
  • ab60720418 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants Lioncash 2018-09-19 03:18:46 -04:00
  • 6b5ea6ee66 A64: Implement BRK Lioncash 2018-09-18 21:17:55 -04:00
  • b915364c16 A64/imm: Add full range of comparison operators to Imm template Lioncash 2018-09-18 20:37:45 -04:00
  • 02150bc0b7 IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed MerryMage 2018-09-18 21:46:17 +01:00
  • 027b0ef725 A64: Implement SCVTF, UCVTF (scalar, fixed-point) MerryMage 2018-09-18 20:45:17 +01:00
  • 8051f60db0 opcodes.inc: Align columns to a tabstop of 4 MerryMage 2018-09-18 20:37:03 +01:00
  • 90193b0e3d IR: Add fbits argument to FixedToFP-related opcodes MerryMage 2018-09-18 20:36:37 +01:00
  • 616a153c16 A64: Implement SQSHL's vector immediate variant Lioncash 2018-09-16 18:11:11 -04:00
  • e8b0f25dff A64: Implement SQSHL's vector register variant Lioncash 2018-09-15 20:30:29 -04:00
  • b14eaaec46 ir: Add opcodes for left signed saturated shifts Lioncash 2018-09-15 15:13:39 -04:00
  • da55ed7b31 branch: Make variables const where applicable Lioncash 2018-09-17 21:28:43 -04:00
  • 867b666285 move_wide: Make variables const where applicable Lioncash 2018-09-17 21:25:31 -04:00
  • 78024a9dc4 load_store_register_unprivileged: Make variables const where applicable Lioncash 2018-09-17 21:23:22 -04:00
  • e45e5da610 load_store_register_immediate: Place conditional bodies on their own line Lioncash 2018-09-17 21:20:15 -04:00
  • b586cf3f56 load_store_load_literal: Make variables const where applicable Lioncash 2018-09-17 21:18:16 -04:00
  • c3a3b9687e data_processing_logical: Move datasize declarations after early-exit conditionals Lioncash 2018-09-17 21:15:59 -04:00
  • ed797e6540 data_processing_conditional_select: Make variables const where applicable Lioncash 2018-09-17 21:07:02 -04:00
  • c82fa5ec5a data_processing_addsub: Move datasize declarations after early-exit conditionals Lioncash 2018-09-17 21:05:32 -04:00
  • f4a66d2477 data_processing_bitfield: Move datasize variables after early-exit conditionals Lioncash 2018-09-17 00:53:38 -04:00
  • 2e0fcd6161 A64: Implement CLS's vector variant Lioncash 2018-09-16 18:41:01 -04:00
  • a2cd643525 emit_x64_vector: Make EmitVectorUnsignedSaturatedAccumulateSigned() internally linked Lioncash 2018-09-15 15:19:50 -04:00
  • c39ea2e3c9 perf_map: Use std::string_view instead of std::string for PerfMapRegister() Lioncash 2018-09-15 14:57:07 -04:00
  • 12243692f5 A64: Implement SQRDMULH (vector), vector variant MerryMage 2018-09-15 13:57:50 +01:00
  • a9ffcf08b1 A64: Implement SQDMULL (vector), vector variant MerryMage 2018-09-15 13:38:37 +01:00
  • 3e447614c6 IR: Add VectorSignedSaturatedDoublingMultiplyLong MerryMage 2018-09-15 13:38:17 +01:00
  • 06b31448aa emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply MerryMage 2018-09-15 09:04:19 +01:00
  • 08c0e017a5 IR: Implement Vector{Signed,Unsigned}Multiply{16,32} MerryMage 2018-09-14 20:06:11 +01:00
  • b6df34cdde backend_x64/a64_interface: Re-enable the constant folding pass Lioncash 2018-09-13 16:37:26 -04:00
  • 06ba397af2 emit_x64_vector_floating_point: Hardware FMA implementation for RSqrtStepFused MerryMage 2018-09-12 21:01:06 +01:00
  • e553c4fe8d emit_x64_vector_floating_point: Hardware FMA implementation of FPVectorRecipStepFused MerryMage 2018-09-12 20:45:39 +01:00
  • 3caeb62ef1 emit_x64_floating_point: Hardware FMA implementation of FPRSqrtStepFused MerryMage 2018-09-12 16:10:18 +01:00
  • 344ee76aba emit_x64_floating_point: Hardware FMA implementation of FPRecipStepFused{32,64} MerryMage 2018-09-12 14:03:46 +01:00
  • 1492573267 emit_x64_vector: SSE implementation of VectorSignedSaturatedAccumulateUnsigned{8,16,32} MerryMage 2018-09-11 19:56:06 +01:00
  • 26df6e5e7b emit_x64_vector: Correct static asserts for < 64-bit type checks in saturated accumulate fallbacks Lioncash 2018-09-10 19:12:43 -04:00
  • a4a26ac226 emit_x64_vector: EmitVectorSignedSaturatedAccumulateUnsigned64: SSE implementation MerryMage 2018-09-10 22:25:28 +01:00
  • a7c66d2d28 emit_x64_vector: Simplify fpsr_qc related code MerryMage 2018-09-10 21:19:58 +01:00
  • 112cff9ab9 A64: Implement CLZ's vector variant Lioncash 2018-09-09 17:46:21 -04:00
  • e739624296 ir: Add opcodes for vector CLZ operations Lioncash 2018-09-09 17:06:47 -04:00
  • d4c37a68a8 A64/translate: VectorZeroUpper for V(64) stores MerryMage 2018-09-09 19:59:02 +01:00
  • b8daa4feac simd_two_register_misc: FNEG (vector) with Q == 0 had dirty upper MerryMage 2018-09-09 19:55:37 +01:00
  • 5653e7637e emit_x64_vector: Remove unnecessary [[maybe_unused]] attributes Lioncash 2018-09-09 13:51:20 -04:00
  • 14e026a7f0 A64: Implement USQADD's scalar and vector variants Lioncash 2018-09-09 03:11:19 -04:00
  • d4a76aaa04 ir: Add opcodes form unsigned saturated accumulations of signed values Lioncash 2018-09-09 02:01:09 -04:00
  • 18ad7f237d A64: Implement SUQADD's scalar and vector variants Lioncash 2018-09-09 01:43:51 -04:00
  • 6f911a26da ir: Add opcodes for signed saturated accumulations of unsigned values Lioncash 2018-09-08 21:08:34 -04:00
  • 9a3d38d2ee A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants Lioncash 2018-09-08 15:18:30 -04:00
  • 6ccfbc9b39 A64: Implement UMULL{2}'s vector by-element variant Lioncash 2018-09-08 14:24:20 -04:00
  • 58e21f175c A64: Implement SMULL{2}'s vector by-element variant Lioncash 2018-09-08 14:16:18 -04:00
  • 134bb02e19 ir/value: Replace includes with forward declarations Lioncash 2018-09-08 20:03:45 -04:00
  • 2c8e07e7d0 ir/cond: Migrate to C++17 nested namespace specifiers Lioncash 2018-09-08 20:10:07 -04:00