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  • f020dbe4ed A64: Implement SQXTUN MerryMage 2018-07-24 16:06:55 +01:00
  • 6918ef7360 microinstruction: Reorganize FPSCR related instruction queries MerryMage 2018-07-24 12:10:57 +01:00
  • a639fa5534 microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() Lioncash 2018-07-22 22:49:35 -04:00
  • 3ca18d8a6d u128: Make Bit() a const-qualified member function Lioncash 2018-07-23 17:52:52 -04:00
  • b2e4c16ef8 A64: Implement FRSQRTS (vector), single/double variant MerryMage 2018-07-23 22:58:52 +01:00
  • 45dc5f74f3 A64: Implement FRSQRTE (vector), single/double variant MerryMage 2018-07-23 22:46:12 +01:00
  • b74d5520f9 A64: Implement FRSQRTS (scalar), single/double variant MerryMage 2018-07-23 22:02:46 +01:00
  • 506e544bfe IR: Implement FPRSqrtStepFused MerryMage 2018-07-23 22:02:28 +01:00
  • 6eb069e80d fp: Implement FPRSqrtStepFused MerryMage 2018-07-23 22:02:12 +01:00
  • b0ff35fcd1 fp: Implement FPNeg MerryMage 2018-07-23 22:01:25 +01:00
  • ca6774ccce process_nan: Add two operand variant MerryMage 2018-07-23 22:00:43 +01:00
  • ace7d2ba50 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant Lioncash 2018-07-23 15:34:00 -04:00
  • 66bb05fc0a emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation MerryMage 2018-07-23 21:10:27 +01:00
  • 070637e0f6 fp: Use a forward declaration in fused.h Lioncash 2018-07-23 15:17:09 -04:00
  • 030820f649 u128: Implement comparison operators in terms of one another Lioncash 2018-07-23 15:11:59 -04:00
  • a04553eb91 tests: Print cpu info MerryMage 2018-07-23 20:22:38 +01:00
  • 76b07d6646 u128: StickyLogicalShiftRight requires special-casing for amount == 64 MerryMage 2018-07-23 20:21:33 +01:00
  • 49c7edf7c6 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant Lioncash 2018-07-22 19:13:10 -04:00
  • c704acafe4 A64: Implement FMUL (by element)'s scalar double/single-precision variant Lioncash 2018-07-22 17:39:16 -04:00
  • 0ce11b7b15 emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64} MerryMage 2018-07-23 16:23:05 +01:00
  • e199887fbc fp: Implement FPMulAdd MerryMage 2018-07-23 16:22:16 +01:00
  • 53a8c15d12 process_nan: Add FPProcessNaNs3 MerryMage 2018-07-23 16:00:21 +01:00
  • 1c8e93e74d block_of_code: Add SysV ABI fifth and sixth parameters MerryMage 2018-07-23 15:59:31 +01:00
  • 1fe8f51c54 u128: Add StickyLogicalShiftRight MerryMage 2018-07-23 15:57:48 +01:00
  • b0afd53ea7 u128: Add Multiply64To128 MerryMage 2018-07-23 15:57:29 +01:00
  • 5566fab29a u128: Add u128::Bit MerryMage 2018-07-23 15:57:05 +01:00
  • 3e62fea003 u128: Add comparison operators MerryMage 2018-07-23 15:56:40 +01:00
  • f17cd6f2c5 unpacked: Use ResidualErrorOnRightShift in FPRoundBase MerryMage 2018-07-23 17:41:13 +01:00
  • 805428e35e fp: Remove MantissaT MerryMage 2018-07-23 11:52:37 +01:00
  • bda86fd167 FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate MerryMage 2018-07-23 11:25:14 +01:00
  • 0a64a66b26 FPRSqrtEstimate: Deduplicate array bounds Lioncash 2018-07-22 17:30:56 -04:00
  • b7bd70fd19 A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV Lioncash 2018-07-22 20:15:52 -04:00
  • 664fb12e21 FPRSqrtEstimate: Use forward declarations where applicable Lioncash 2018-07-22 17:27:39 -04:00
  • 3447c82656 translate: Return by bool in helpers where applicable Lioncash 2018-07-22 16:55:40 -04:00
  • d65b056eba Simplify fallback case for EmitVectorSetElement64() Lioncash 2018-07-22 17:20:11 -04:00
  • 6087c2af6f emit_x64_floating_point: s/Esimate/Estimate/ MerryMage 2018-07-22 21:49:08 +01:00
  • f837ce8e78 simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant MerryMage 2018-07-22 18:19:16 +01:00
  • bde58b04d4 IR: Implement FPRSqrtEstimate MerryMage 2018-07-22 18:18:22 +01:00
  • 16061c28f3 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant MerryMage 2018-07-22 17:25:58 +01:00
  • 55eaa16615 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT MerryMage 2018-07-22 16:16:26 +01:00
  • edd795e991 a64_emit_x64: Fix stack misalignment on Windows for 128-bit exclusive writes MerryMage 2018-07-22 15:05:53 +01:00
  • 04b4c8b0cf emit_x64_aes: Eliminate extraneous usage of a scratch register in EmitAESInverseMixColumns() Lioncash 2018-07-21 20:26:01 -04:00
  • e5d80e998e A64: Implement SADDLV Lioncash 2018-07-21 20:16:39 -04:00
  • a1bc8ddb53 A64: Implement UADDLV Lioncash 2018-07-21 19:53:21 -04:00
  • 1dc1e3dcd8 fp: Use forward declarations where applicable Lioncash 2018-07-21 14:01:19 -04:00
  • 46cb0d813b emit_x64_vector: Append 'v' prefix onto movq in AVX path Lioncash 2018-07-21 21:33:20 -04:00
  • 4606a081c9 A64: The A64SetTPIDR IR instruction writes to a system register and should not be eliminated by the dead code elimination pass. Subv 2018-07-20 20:20:20 -05:00
  • b53127600b fp: A64::FPCR -> FP::FPCR MerryMage 2018-07-17 19:53:21 +01:00
  • 084bf63a10 bit_util: Implement ClearBits and ModifyBits MerryMage 2018-07-17 19:38:34 +01:00
  • 699c5f36d5 system: Simplify static_cast MerryMage 2018-07-19 12:03:02 +01:00
  • d4688b7f2d externals: Update Xbyak to 5.65 Lioncash 2018-07-17 21:57:43 -04:00
  • 3f602129f4 system: Ensure value of CNTPCT_EL0 is accurate MerryMage 2018-07-19 01:40:51 +01:00
  • 84affdb260 safe_ops: Avoid cases where shift bases are invalid with signed values Lioncash 2018-07-17 14:53:50 -04:00
  • d0274f412a safe_ops: Avoid signed overflow in Negate() Lioncash 2018-07-17 14:39:07 -04:00
  • af3e23b224 simd_scalar_shift_by_immediate: Implement FCVT{ZS, ZU} (vector, fixed-point)'s scalar double/single-precision variant Lioncash 2018-07-17 12:52:13 -04:00
  • 91abf87169 simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants Lioncash 2018-07-17 12:27:18 -04:00
  • 5b39e8dcf8 tests: Silence warnings in skyeye code Lioncash 2018-07-17 11:43:35 -04:00
  • 0ec8dac660 emit_x64: Remove FPSCR_RoundTowardsZero() virtual function from EmitContext struct Lioncash 2018-07-17 14:05:54 -04:00
  • fd92e2f186 emit_x64: Add missing <array> include Lioncash 2018-07-17 13:57:25 -04:00
  • f939bd0228 emit_x64_vector{_floating_point}: Add helper alias for sizing arrays relative to vector width Lioncash 2018-07-15 20:16:11 -04:00
  • 58f3399032 A64/PopRSBHint: Prevent RETing to a guest PC of ~0ull from crashing the jit MerryMage 2018-07-16 18:24:29 +01:00
  • 4525209bab tests: Add FABD test MerryMage 2018-07-16 16:55:26 +01:00
  • e18fca17dc A64: Implement FABD in terms of existing IR instructions MerryMage 2018-07-16 16:51:16 +01:00
  • 1dbe9d95e6 FPRoundInt: Final FPRound based on new sign MerryMage 2018-07-16 15:07:26 +01:00
  • 83be491875 emit_x64_floating_point: SSE4.1 implementation of EmitFPRound MerryMage 2018-07-16 14:22:29 +01:00
  • a40127a054 A64: Implement FRINTX, FRINTI (scalar) MerryMage 2018-07-16 14:10:06 +01:00
  • 962fa3b65e A64: Implement FRINTP, FRINTM, FRINTZ (scalar) MerryMage 2018-07-16 13:58:58 +01:00
  • 5200bf41cf A64: Implement FRINTN (scalar) MerryMage 2018-07-16 13:55:19 +01:00
  • 8718dc1692 A64: Implement FRINTA (scalar) MerryMage 2018-07-16 13:49:32 +01:00
  • b228694012 IR: Implement FPRoundInt MerryMage 2018-07-16 13:49:15 +01:00
  • e24054f4d7 fp: Implement FPRoundInt MerryMage 2018-07-16 13:48:30 +01:00
  • f876e4afa2 fp: Implement FPProcessNaN MerryMage 2018-07-16 13:48:13 +01:00
  • 591adee443 fp/info: Add DefaultNaN MerryMage 2018-07-16 13:47:46 +01:00
  • 797e18cd97 fp: Move FPToFixed to its own file MerryMage 2018-07-16 12:51:36 +01:00
  • 295deb4035 a64_jit_state: Add FPSR.QC flag MerryMage 2018-07-15 23:19:35 +01:00
  • 7797bc2fb2 emit_x64_vector: Use non-scratch Use* variants of registers within EmitVectorUnsignedAbsoluteDifference() Lioncash 2018-07-15 22:06:29 -04:00
  • f7f83b76b7 simd_scalar_two_register_misc: Implement scalar double/single-precision variants of FCM{EQ, GE, GT, LE, LT} (zero) Lioncash 2018-07-15 19:50:32 -04:00
  • 9db6d1e98b translate_arm: Remove unnecessary rotr() function Lioncash 2018-07-15 21:24:23 -04:00
  • c167715336 Merge pull request #309 from lioncash/typename Merry 2018-07-16 10:18:03 +01:00
  • 9f8a44c982 cast_util: Remove unnecessary typename Lioncash 2018-07-15 19:06:47 -04:00
  • 89e43867c1 A64: Implement FADDP (scalar) MerryMage 2018-07-15 22:46:27 +01:00
  • 33fa65de23 A64: Implement FADDP (vector) MerryMage 2018-07-15 22:41:10 +01:00
  • 9dba273a8c A64: Implement SADDLP MerryMage 2018-07-15 18:48:11 +01:00
  • 70ff2d73b5 A64: Implement UADDLP MerryMage 2018-07-15 18:26:54 +01:00
  • 5563bbbd79 A64: Implement EXT MerryMage 2018-07-15 17:47:32 +01:00
  • d50eaedaa7 Merge pull request #289 from MerryMage/fptofixed Merry 2018-07-15 17:12:52 +01:00
  • 304cc7f61e emit_x64_floating_point: SSE4.1 implementation for FP{Double,Single}ToFixed{S,U}{32,64} MerryMage 2018-07-15 17:03:35 +01:00
  • 3d9677d094 A64: Implement FCVTMU (scalar) MerryMage 2018-06-30 12:21:07 +01:00
  • 79c9018d60 A64: Implement FCVTMS (scalar) MerryMage 2018-06-30 12:19:38 +01:00
  • 49c4499a87 A64: Implement FCVTPU (scalar) MerryMage 2018-06-30 12:19:02 +01:00
  • af661ef5a6 A64: Implement FCVTPS (scalar) MerryMage 2018-06-30 12:18:40 +01:00
  • 27319822bb A64: Implement FCVTAU (scalar) MerryMage 2018-06-30 12:17:37 +01:00
  • c0c7a26314 A64: Implement FCVTAS (scalar) MerryMage 2018-06-30 12:15:35 +01:00
  • a1965a74a0 A64: Implement FCVTNU (scalar) MerryMage 2018-06-30 11:39:30 +01:00
  • 7d36dbcdfd A64: Implement FCVTNS (scalar) MerryMage 2018-06-30 11:39:07 +01:00
  • 617ca0adf0 floating_point_conversion_integer: Refactor implementation of FCVTZS_float_int and FCVTZU_float_int MerryMage 2018-06-30 11:36:46 +01:00
  • caaf36dfd6 IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64} MerryMage 2018-06-30 10:49:47 +01:00
  • 760cc3ca89 EmitContext: Expose FPCR MerryMage 2018-07-15 14:23:50 +01:00
  • 9571269552 fp/op: Implement FPToFixed MerryMage 2018-06-29 19:34:46 +01:00
  • 8087e8df05 mantissa_util: Implement ResidualErrorOnRightShift MerryMage 2018-06-29 18:52:48 +01:00