mirror of
https://github.com/azahar-emu/dynarmic.git
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88 lines
3.0 KiB
C++
88 lines
3.0 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2020 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_arm.h"
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namespace Dynarmic::A32 {
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namespace {
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enum class Accumulating {
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None,
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Accumulate
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};
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enum class Rounding {
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None,
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Round,
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};
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IR::U128 PerformRoundingCorrection(ArmTranslatorVisitor& v, size_t esize, u64 round_value, IR::U128 original, IR::U128 shifted) {
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const auto round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value));
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const auto round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(original, round_const), round_const);
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return v.ir.VectorSub(esize, shifted, round_correction);
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}
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std::pair<size_t, size_t> ElementSizeAndShiftAmount(bool L, size_t imm6) {
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if (L) {
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return {64, 64 - imm6};
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}
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const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3);
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const size_t shift_amount = (esize * 2) - imm6;
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return {esize, shift_amount};
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}
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bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm,
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Accumulating accumulate, Rounding rounding) {
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
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return v.UndefinedInstruction();
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}
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// Technically just a related encoding (One register and modified immediate instructions)
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if (!L && Common::Bits<3, 5>(imm6) == 0) {
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return v.UndefinedInstruction();
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}
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const auto [esize, shift_amount] = ElementSizeAndShiftAmount(L, imm6);
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto reg_m = v.ir.GetVector(m);
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auto result = U ? v.ir.VectorLogicalShiftRight(esize, reg_m, static_cast<u8>(shift_amount))
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: v.ir.VectorArithmeticShiftRight(esize, reg_m, static_cast<u8>(shift_amount));
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if (rounding == Rounding::Round) {
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const u64 round_value = 1ULL << (shift_amount - 1);
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result = PerformRoundingCorrection(v, esize, round_value, reg_m, result);
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}
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if (accumulate == Accumulating::Accumulate) {
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const auto reg_d = v.ir.GetVector(d);
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result = v.ir.VectorAdd(esize, result, reg_d);
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}
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v.ir.SetVector(d, result);
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return true;
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}
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} // Anonymous namespace
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bool ArmTranslatorVisitor::asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
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return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm,
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Accumulating::None, Rounding::None);
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}
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bool ArmTranslatorVisitor::asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
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return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm,
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Accumulating::Accumulate, Rounding::None);
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}
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bool ArmTranslatorVisitor::asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
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return ShiftRight(*this, U, D, imm6, Vd, L, Q, M, Vm,
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Accumulating::None, Rounding::Round);
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}
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} // namespace Dynarmic::A32
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