mirror of
https://github.com/azahar-emu/dynarmic.git
synced 2026-03-20 12:41:02 +01:00
4ae4750b5a
Previously we just retrieved the last stored FPSR and used that when the guest asks for the current FPSR. This is incorrect behaviour. We failed to take into account the current state of the host FPSR. Here we take this into account. This bug was discovered via #795.
520 lines
20 KiB
C++
520 lines
20 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2022 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include <mcl/bit_cast.hpp>
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#include <oaknut/oaknut.hpp>
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#include "dynarmic/backend/arm64/a64_jitstate.h"
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#include "dynarmic/backend/arm64/abi.h"
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#include "dynarmic/backend/arm64/emit_arm64.h"
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#include "dynarmic/backend/arm64/emit_context.h"
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#include "dynarmic/backend/arm64/fpsr_manager.h"
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#include "dynarmic/backend/arm64/reg_alloc.h"
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#include "dynarmic/interface/halt_reason.h"
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#include "dynarmic/ir/basic_block.h"
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#include "dynarmic/ir/microinstruction.h"
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#include "dynarmic/ir/opcodes.h"
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namespace Dynarmic::Backend::Arm64 {
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using namespace oaknut::util;
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oaknut::Label EmitA64Cond(oaknut::CodeGenerator& code, EmitContext&, IR::Cond cond) {
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oaknut::Label pass;
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// TODO: Flags in host flags
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code.LDR(Wscratch0, Xstate, offsetof(A64JitState, cpsr_nzcv));
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code.MSR(oaknut::SystemReg::NZCV, Xscratch0);
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code.B(static_cast<oaknut::Cond>(cond), pass);
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return pass;
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::Terminal terminal, IR::LocationDescriptor initial_location, bool is_single_step);
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void EmitA64Terminal(oaknut::CodeGenerator&, EmitContext&, IR::Term::Interpret, IR::LocationDescriptor, bool) {
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ASSERT_FALSE("Interpret should never be emitted.");
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::ReturnToDispatch, IR::LocationDescriptor, bool) {
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EmitRelocation(code, ctx, LinkTarget::ReturnToDispatcher);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::LinkBlock terminal, IR::LocationDescriptor, bool is_single_step) {
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oaknut::Label fail;
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if (ctx.conf.HasOptimization(OptimizationFlag::BlockLinking) && !is_single_step) {
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if (ctx.conf.enable_cycle_counting) {
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code.CMP(Xticks, 0);
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code.B(LE, fail);
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EmitBlockLinkRelocation(code, ctx, terminal.next, BlockRelocationType::Branch);
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} else {
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code.LDAR(Wscratch0, Xhalt);
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code.CBNZ(Wscratch0, fail);
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EmitBlockLinkRelocation(code, ctx, terminal.next, BlockRelocationType::Branch);
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}
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}
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code.l(fail);
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code.MOV(Xscratch0, A64::LocationDescriptor{terminal.next}.PC());
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code.STR(Xscratch0, Xstate, offsetof(A64JitState, pc));
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EmitRelocation(code, ctx, LinkTarget::ReturnToDispatcher);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::LinkBlockFast terminal, IR::LocationDescriptor, bool is_single_step) {
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if (ctx.conf.HasOptimization(OptimizationFlag::BlockLinking) && !is_single_step) {
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EmitBlockLinkRelocation(code, ctx, terminal.next, BlockRelocationType::Branch);
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}
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code.MOV(Xscratch0, A64::LocationDescriptor{terminal.next}.PC());
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code.STR(Xscratch0, Xstate, offsetof(A64JitState, pc));
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EmitRelocation(code, ctx, LinkTarget::ReturnToDispatcher);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::PopRSBHint, IR::LocationDescriptor, bool is_single_step) {
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if (ctx.conf.HasOptimization(OptimizationFlag::ReturnStackBuffer) && !is_single_step) {
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oaknut::Label fail;
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code.MOV(Wscratch0, A64::LocationDescriptor::fpcr_mask);
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code.LDR(W0, Xstate, offsetof(A64JitState, fpcr));
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code.LDR(X1, Xstate, offsetof(A64JitState, pc));
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code.AND(W0, W0, Wscratch0);
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code.AND(X1, X1, A64::LocationDescriptor::pc_mask);
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code.LSL(X0, X0, A64::LocationDescriptor::fpcr_shift);
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code.ORR(X0, X0, X1);
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code.LDR(Wscratch2, SP, offsetof(StackLayout, rsb_ptr));
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code.AND(Wscratch2, Wscratch2, RSBIndexMask);
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code.ADD(X2, SP, Xscratch2);
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code.SUB(Wscratch2, Wscratch2, sizeof(RSBEntry));
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code.STR(Wscratch2, SP, offsetof(StackLayout, rsb_ptr));
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code.LDP(Xscratch0, Xscratch1, X2, offsetof(StackLayout, rsb));
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code.CMP(X0, Xscratch0);
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code.B(NE, fail);
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code.BR(Xscratch1);
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code.l(fail);
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}
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EmitRelocation(code, ctx, LinkTarget::ReturnToDispatcher);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::FastDispatchHint, IR::LocationDescriptor, bool) {
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EmitRelocation(code, ctx, LinkTarget::ReturnToDispatcher);
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// TODO: Implement FastDispatchHint optimization
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::If terminal, IR::LocationDescriptor initial_location, bool is_single_step) {
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oaknut::Label pass = EmitA64Cond(code, ctx, terminal.if_);
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EmitA64Terminal(code, ctx, terminal.else_, initial_location, is_single_step);
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code.l(pass);
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EmitA64Terminal(code, ctx, terminal.then_, initial_location, is_single_step);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::CheckBit terminal, IR::LocationDescriptor initial_location, bool is_single_step) {
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oaknut::Label fail;
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code.LDRB(Wscratch0, SP, offsetof(StackLayout, check_bit));
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code.CBZ(Wscratch0, fail);
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EmitA64Terminal(code, ctx, terminal.then_, initial_location, is_single_step);
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code.l(fail);
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EmitA64Terminal(code, ctx, terminal.else_, initial_location, is_single_step);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::CheckHalt terminal, IR::LocationDescriptor initial_location, bool is_single_step) {
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oaknut::Label fail;
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code.LDAR(Wscratch0, Xhalt);
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code.CBNZ(Wscratch0, fail);
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EmitA64Terminal(code, ctx, terminal.else_, initial_location, is_single_step);
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code.l(fail);
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EmitRelocation(code, ctx, LinkTarget::ReturnToDispatcher);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::Terminal terminal, IR::LocationDescriptor initial_location, bool is_single_step) {
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boost::apply_visitor([&](const auto& t) { EmitA64Terminal(code, ctx, t, initial_location, is_single_step); }, terminal);
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}
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void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx) {
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const A64::LocationDescriptor location{ctx.block.Location()};
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EmitA64Terminal(code, ctx, ctx.block.GetTerminal(), location.SetSingleStepping(false), location.SingleStepping());
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}
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void EmitA64ConditionFailedTerminal(oaknut::CodeGenerator& code, EmitContext& ctx) {
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const A64::LocationDescriptor location{ctx.block.Location()};
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EmitA64Terminal(code, ctx, IR::Term::LinkBlock{ctx.block.ConditionFailedLocation()}, location.SetSingleStepping(false), location.SingleStepping());
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}
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void EmitA64CheckMemoryAbort(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, oaknut::Label& end) {
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if (!ctx.conf.check_halt_on_memory_access) {
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return;
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}
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const A64::LocationDescriptor current_location{IR::LocationDescriptor{inst->GetArg(0).GetU64()}};
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code.LDAR(Xscratch0, Xhalt);
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code.TST(Xscratch0, static_cast<u32>(HaltReason::MemoryAbort));
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code.B(EQ, end);
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code.MOV(Xscratch0, current_location.PC());
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code.STR(Xscratch0, Xstate, offsetof(A64JitState, pc));
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EmitRelocation(code, ctx, LinkTarget::ReturnFromRunCode);
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}
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template<>
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void EmitIR<IR::Opcode::A64SetCheckBit>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (args[0].IsImmediate()) {
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if (args[0].GetImmediateU1()) {
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code.MOV(Wscratch0, 1);
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code.STRB(Wscratch0, SP, offsetof(StackLayout, check_bit));
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} else {
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code.STRB(WZR, SP, offsetof(StackLayout, check_bit));
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}
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} else {
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auto Wbit = ctx.reg_alloc.ReadW(args[0]);
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RegAlloc::Realize(Wbit);
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code.STRB(Wbit, SP, offsetof(StackLayout, check_bit));
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}
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}
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template<>
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void EmitIR<IR::Opcode::A64GetCFlag>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto Wflag = ctx.reg_alloc.WriteW(inst);
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RegAlloc::Realize(Wflag);
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code.LDR(Wflag, Xstate, offsetof(A64JitState, cpsr_nzcv));
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code.AND(Wflag, Wflag, 1 << 29);
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}
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template<>
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void EmitIR<IR::Opcode::A64GetNZCVRaw>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto Wnzcv = ctx.reg_alloc.WriteW(inst);
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RegAlloc::Realize(Wnzcv);
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code.LDR(Wnzcv, Xstate, offsetof(A64JitState, cpsr_nzcv));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetNZCVRaw>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Wnzcv = ctx.reg_alloc.ReadW(args[0]);
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RegAlloc::Realize(Wnzcv);
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code.STR(Wnzcv, Xstate, offsetof(A64JitState, cpsr_nzcv));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetNZCV>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Wnzcv = ctx.reg_alloc.ReadW(args[0]);
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RegAlloc::Realize(Wnzcv);
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code.STR(Wnzcv, Xstate, offsetof(A64JitState, cpsr_nzcv));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetW>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
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auto Wresult = ctx.reg_alloc.WriteW(inst);
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RegAlloc::Realize(Wresult);
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// TODO: Detect if Gpr vs Fpr is more appropriate
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code.LDR(Wresult, Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetX>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
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auto Xresult = ctx.reg_alloc.WriteX(inst);
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RegAlloc::Realize(Xresult);
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// TODO: Detect if Gpr vs Fpr is more appropriate
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code.LDR(Xresult, Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetS>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
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auto Sresult = ctx.reg_alloc.WriteS(inst);
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RegAlloc::Realize(Sresult);
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code.LDR(Sresult, Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetD>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
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auto Dresult = ctx.reg_alloc.WriteD(inst);
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RegAlloc::Realize(Dresult);
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code.LDR(Dresult, Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetQ>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
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auto Qresult = ctx.reg_alloc.WriteQ(inst);
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RegAlloc::Realize(Qresult);
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code.LDR(Qresult, Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetSP>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto Xresult = ctx.reg_alloc.WriteX(inst);
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RegAlloc::Realize(Xresult);
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code.LDR(Xresult, Xstate, offsetof(A64JitState, sp));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetFPCR>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto Wresult = ctx.reg_alloc.WriteW(inst);
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RegAlloc::Realize(Wresult);
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code.LDR(Wresult, Xstate, offsetof(A64JitState, fpcr));
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}
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template<>
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void EmitIR<IR::Opcode::A64GetFPSR>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
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auto Wresult = ctx.reg_alloc.WriteW(inst);
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RegAlloc::Realize(Wresult);
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ctx.fpsr.GetFpsr(Wresult);
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}
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template<>
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void EmitIR<IR::Opcode::A64SetW>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Wvalue = ctx.reg_alloc.ReadW(args[1]);
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RegAlloc::Realize(Wvalue);
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// TODO: Detect if Gpr vs Fpr is more appropriate
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code.MOV(*Wvalue, Wvalue);
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code.STR(Wvalue->toX(), Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetX>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Xvalue = ctx.reg_alloc.ReadX(args[1]);
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RegAlloc::Realize(Xvalue);
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// TODO: Detect if Gpr vs Fpr is more appropriate
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code.STR(Xvalue, Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetS>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
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auto Svalue = ctx.reg_alloc.ReadS(args[1]);
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RegAlloc::Realize(Svalue);
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code.FMOV(Svalue, Svalue);
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code.STR(Svalue->toQ(), Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetD>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
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auto Dvalue = ctx.reg_alloc.ReadD(args[1]);
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RegAlloc::Realize(Dvalue);
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code.FMOV(Dvalue, Dvalue);
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code.STR(Dvalue->toQ(), Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetQ>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
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auto Qvalue = ctx.reg_alloc.ReadQ(args[1]);
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RegAlloc::Realize(Qvalue);
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code.STR(Qvalue, Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetSP>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Xvalue = ctx.reg_alloc.ReadX(args[0]);
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RegAlloc::Realize(Xvalue);
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code.STR(Xvalue, Xstate, offsetof(A64JitState, sp));
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}
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template<>
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void EmitIR<IR::Opcode::A64SetFPCR>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Wvalue = ctx.reg_alloc.ReadW(args[0]);
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RegAlloc::Realize(Wvalue);
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code.STR(Wvalue, Xstate, offsetof(A64JitState, fpcr));
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code.MSR(oaknut::SystemReg::FPCR, Wvalue->toX());
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}
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template<>
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void EmitIR<IR::Opcode::A64SetFPSR>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Wvalue = ctx.reg_alloc.ReadW(args[0]);
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RegAlloc::Realize(Wvalue);
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code.STR(Wvalue, Xstate, offsetof(A64JitState, fpsr));
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code.MSR(oaknut::SystemReg::FPSR, Wvalue->toX());
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}
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template<>
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void EmitIR<IR::Opcode::A64SetPC>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto Xvalue = ctx.reg_alloc.ReadX(args[0]);
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RegAlloc::Realize(Xvalue);
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code.STR(Xvalue, Xstate, offsetof(A64JitState, pc));
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}
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template<>
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void EmitIR<IR::Opcode::A64CallSupervisor>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ctx.reg_alloc.PrepareForCall();
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if (ctx.conf.enable_cycle_counting) {
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code.LDR(X1, SP, offsetof(StackLayout, cycles_to_run));
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code.SUB(X1, X1, Xticks);
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EmitRelocation(code, ctx, LinkTarget::AddTicks);
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}
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|
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code.MOV(W1, args[0].GetImmediateU32());
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EmitRelocation(code, ctx, LinkTarget::CallSVC);
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|
|
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if (ctx.conf.enable_cycle_counting) {
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EmitRelocation(code, ctx, LinkTarget::GetTicksRemaining);
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code.STR(X0, SP, offsetof(StackLayout, cycles_to_run));
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|
code.MOV(Xticks, X0);
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|
}
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}
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|
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template<>
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void EmitIR<IR::Opcode::A64ExceptionRaised>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
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|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
ctx.reg_alloc.PrepareForCall();
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|
|
|
if (ctx.conf.enable_cycle_counting) {
|
|
code.LDR(X1, SP, offsetof(StackLayout, cycles_to_run));
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|
code.SUB(X1, X1, Xticks);
|
|
EmitRelocation(code, ctx, LinkTarget::AddTicks);
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|
}
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|
|
|
code.MOV(X1, args[0].GetImmediateU64());
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|
code.MOV(X2, args[1].GetImmediateU64());
|
|
EmitRelocation(code, ctx, LinkTarget::ExceptionRaised);
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|
|
|
if (ctx.conf.enable_cycle_counting) {
|
|
EmitRelocation(code, ctx, LinkTarget::GetTicksRemaining);
|
|
code.STR(X0, SP, offsetof(StackLayout, cycles_to_run));
|
|
code.MOV(Xticks, X0);
|
|
}
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64DataCacheOperationRaised>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
ctx.reg_alloc.PrepareForCall({}, args[1], args[2]);
|
|
EmitRelocation(code, ctx, LinkTarget::DataCacheOperationRaised);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64InstructionCacheOperationRaised>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
ctx.reg_alloc.PrepareForCall({}, args[0], args[1]);
|
|
EmitRelocation(code, ctx, LinkTarget::InstructionCacheOperationRaised);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64DataSynchronizationBarrier>(oaknut::CodeGenerator& code, EmitContext&, IR::Inst*) {
|
|
code.DSB(oaknut::BarrierOp::SY);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64DataMemoryBarrier>(oaknut::CodeGenerator& code, EmitContext&, IR::Inst*) {
|
|
code.DMB(oaknut::BarrierOp::SY);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64InstructionSynchronizationBarrier>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*) {
|
|
if (!ctx.conf.hook_isb) {
|
|
return;
|
|
}
|
|
|
|
ctx.reg_alloc.PrepareForCall();
|
|
EmitRelocation(code, ctx, LinkTarget::InstructionSynchronizationBarrierRaised);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64GetCNTFRQ>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto Xvalue = ctx.reg_alloc.WriteX(inst);
|
|
RegAlloc::Realize(Xvalue);
|
|
code.MOV(Xvalue, ctx.conf.cntfreq_el0);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64GetCNTPCT>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
ctx.reg_alloc.PrepareForCall();
|
|
if (!ctx.conf.wall_clock_cntpct && ctx.conf.enable_cycle_counting) {
|
|
code.LDR(X1, SP, offsetof(StackLayout, cycles_to_run));
|
|
code.SUB(X1, X1, Xticks);
|
|
EmitRelocation(code, ctx, LinkTarget::AddTicks);
|
|
EmitRelocation(code, ctx, LinkTarget::GetTicksRemaining);
|
|
code.STR(X0, SP, offsetof(StackLayout, cycles_to_run));
|
|
code.MOV(Xticks, X0);
|
|
}
|
|
EmitRelocation(code, ctx, LinkTarget::GetCNTPCT);
|
|
ctx.reg_alloc.DefineAsRegister(inst, X0);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64GetCTR>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto Wvalue = ctx.reg_alloc.WriteW(inst);
|
|
RegAlloc::Realize(Wvalue);
|
|
code.MOV(Wvalue, ctx.conf.ctr_el0);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64GetDCZID>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto Wvalue = ctx.reg_alloc.WriteW(inst);
|
|
RegAlloc::Realize(Wvalue);
|
|
code.MOV(Wvalue, ctx.conf.dczid_el0);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64GetTPIDR>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto Xvalue = ctx.reg_alloc.WriteX(inst);
|
|
RegAlloc::Realize(Xvalue);
|
|
code.MOV(Xscratch0, mcl::bit_cast<u64>(ctx.conf.tpidr_el0));
|
|
code.LDR(Xvalue, Xscratch0);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64GetTPIDRRO>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto Xvalue = ctx.reg_alloc.WriteX(inst);
|
|
RegAlloc::Realize(Xvalue);
|
|
code.MOV(Xscratch0, mcl::bit_cast<u64>(ctx.conf.tpidrro_el0));
|
|
code.LDR(Xvalue, Xscratch0);
|
|
}
|
|
|
|
template<>
|
|
void EmitIR<IR::Opcode::A64SetTPIDR>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
auto Xvalue = ctx.reg_alloc.ReadX(args[0]);
|
|
RegAlloc::Realize(Xvalue);
|
|
code.MOV(Xscratch0, mcl::bit_cast<u64>(ctx.conf.tpidr_el0));
|
|
code.STR(Xvalue, Xscratch0);
|
|
}
|
|
|
|
} // namespace Dynarmic::Backend::Arm64
|