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https://github.com/azahar-emu/dynarmic.git
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64 lines
1.9 KiB
C++
64 lines
1.9 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2019 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::CFINV() {
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const IR::U32 nzcv = ir.GetNZCVRaw();
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const IR::U32 result = ir.Eor(nzcv, ir.Imm32(0x20000000));
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ir.SetNZCVRaw(result);
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return true;
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}
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bool TranslatorVisitor::RMIF(Imm<6> lsb, Reg Rn, Imm<4> mask) {
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const u32 mask_value = mask.ZeroExtend();
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// If no bits are to be moved into the NZCV bits, then we
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// just preserve the bits and do no extra work.
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if (mask_value == 0) {
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ir.SetNZCVRaw(ir.GetNZCVRaw());
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return true;
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}
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const IR::U64 tmp_reg = ir.GetX(Rn);
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const IR::U64 rotated = ir.RotateRight(tmp_reg, ir.Imm8(lsb.ZeroExtend<u8>()));
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const IR::U32 shifted = ir.LeastSignificantWord(ir.LogicalShiftLeft(rotated, ir.Imm8(28)));
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// On the other hand, if all mask bits are set, then we move all four
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// relevant bits in the source register to the NZCV bits.
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if (mask_value == 0b1111) {
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ir.SetNZCVRaw(shifted);
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return true;
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}
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// Determine which bits from the PSTATE will be preserved during the operation.
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u32 preservation_mask = 0;
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if ((mask_value & 0b1000) == 0) {
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preservation_mask |= 1U << 31;
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}
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if ((mask_value & 0b0100) == 0) {
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preservation_mask |= 1U << 30;
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}
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if ((mask_value & 0b0010) == 0) {
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preservation_mask |= 1U << 29;
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}
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if ((mask_value & 0b0001) == 0) {
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preservation_mask |= 1U << 28;
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}
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const IR::U32 masked = ir.And(shifted, ir.Imm32(~preservation_mask));
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const IR::U32 nzcv = ir.And(ir.GetNZCVRaw(), ir.Imm32(preservation_mask));
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const IR::U32 result = ir.Or(nzcv, masked);
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ir.SetNZCVRaw(result);
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return true;
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}
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} // namespace Dynarmic::A64
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