Lioncash fcae4e2418 simd_three_different: Deduplicate common implementations ...

Generally, the only difference between the signed variants and the
unsigned variants is whether or not we use a sign-extension or
zero-extension, so we can simply use common functions to implement both
cases without totally duplicating code twice here.

2020-04-22 20:46:19 +01:00

..

branch.cpp

Implement DC instructions

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data_processing_addsub.cpp

General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

2020-04-22 20:44:38 +01:00

data_processing_bitfield.cpp

A64: Implement EXTR

2020-04-22 20:46:12 +01:00

data_processing_conditional_compare.cpp

A64: Implement CCMP (immediate)

2020-04-22 20:46:13 +01:00

data_processing_conditional_select.cpp

General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

2020-04-22 20:44:38 +01:00

data_processing_crc32.cpp

A64: Implement CRC32

2020-04-22 20:46:12 +01:00

data_processing_logical.cpp

General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

2020-04-22 20:44:38 +01:00

data_processing_multiply.cpp

A64: Move SDIV and UDIV out of data_processing_multiply.cpp

2020-04-22 20:46:13 +01:00

data_processing_pcrel.cpp

General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

2020-04-22 20:44:38 +01:00

data_processing_register.cpp

A64: Move SDIV and UDIV out of data_processing_multiply.cpp

2020-04-22 20:46:13 +01:00

data_processing_shift.cpp

General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

2020-04-22 20:44:38 +01:00

exception_generating.cpp

Implement DC instructions

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floating_point_compare.cpp

IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them

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floating_point_conditional_compare.cpp

A64: Implement FCCMPE

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floating_point_conditional_select.cpp

A64: Implement FCSEL

2020-04-22 20:46:13 +01:00

floating_point_conversion_fixed_point.cpp

A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)

2020-04-22 20:46:15 +01:00

floating_point_conversion_integer.cpp

floating_point_conversion_integer: Handle S64/U64 -> F32 conversions in SCVTF_float_int and UCVTF_float_int

2020-04-22 20:46:19 +01:00

floating_point_data_processing_one_register.cpp

A64: Implement FSQRT (scalar)

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floating_point_data_processing_three_register.cpp

A64: Implement FNMSUB

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floating_point_data_processing_two_register.cpp

A64: Implement FMINNM (scalar)

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impl.cpp

translate: zero extend result in Vpart when storing to lower part of vector

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impl.h

A64: Implement load/store single structure instructions

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load_store_exclusive.cpp

Exclusive fixups

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load_store_load_literal.cpp

A64: Implement LDR (literal, SIMD&FP)

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load_store_multiple_structures.cpp

load_store_multiple_structures: Improve IR codegen for selem == 1 case

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load_store_register_immediate.cpp

A64: Add missing decoding for PRFM (unscaled offset)

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load_store_register_pair.cpp

A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)

2020-04-22 20:44:38 +01:00

load_store_register_register_offset.cpp

A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)

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load_store_register_unprivileged.cpp

General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

2020-04-22 20:44:38 +01:00

load_store_single_structure.cpp

A64: Implement load/store single structure instructions

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move_wide.cpp

General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

2020-04-22 20:44:38 +01:00

simd_across_lanes.cpp

A64: Implement ADDV

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simd_aes.cpp

A64: Implement AESD

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simd_copy.cpp

A64: Implement DUP (element), scalar variant

2020-04-22 20:46:14 +01:00

simd_crypto_four_register.cpp

A64: Implement SM3SS1

2020-04-22 20:46:16 +01:00

simd_crypto_three_register.cpp

A64: Implement SM3TT2B

2020-04-22 20:46:16 +01:00

simd_extract.cpp

A64: Implement EXT

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simd_modified_immediate.cpp

A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated

2020-04-22 20:46:15 +01:00

simd_permute.cpp

A64: Implement UZP1 and UZP2

2020-04-22 20:46:17 +01:00

simd_scalar_pairwise.cpp

A64: Implement ADDP (scalar)

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simd_scalar_shift_by_immediate.cpp

A64: Implement URSHR (scalar) and URSRA (scalar)

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simd_scalar_three_same.cpp

A64: Implement scalar double/single-precision variants of FACGE, FACGT, FCMEQ, FCMGE, FCMGT

2020-04-22 20:46:18 +01:00

simd_scalar_two_register_misc.cpp

simd_scalar_two_register_misc: Handle 64-bit case in SCVTF and UCVTF's scalar double/single-precision variant

2020-04-22 20:46:18 +01:00

simd_sha512.cpp

A64: Implement SM4EKEY

2020-04-22 20:46:17 +01:00

simd_sha.cpp

A64: Implement SHA256H and SHA256H2

2020-04-22 20:46:16 +01:00

simd_shift_by_immediate.cpp

simd_shift_by_immediate: Merge signed/unsigned helper functions

2020-04-22 20:46:16 +01:00

simd_three_different.cpp

simd_three_different: Deduplicate common implementations

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simd_three_same.cpp

simd_three_same: Join FPAbsoluteComparison() into FPCompareRegister()

2020-04-22 20:46:19 +01:00

simd_two_register_misc.cpp

simd_two_register_misc: Utilize FPVectorAbs in FABS implementations

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simd_vector_x_indexed_element.cpp

A64: Implement MLS (by element)

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sys_dc.cpp

Correct typo in DataCacheOperation enum

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system.cpp

A64: system: Use an enum class for MRS/MSR register encodings

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