diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index f08eea8bcae..fd3e925e9a3 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -323,7 +323,7 @@
   (and (match_code "mem")
        (match_test "aarch64_simd_mem_operand_p (op)")))
 
-(define_memory_constraint "Utq"
+(define_relaxed_memory_constraint "Utq"
   "@internal
    An address valid for loading or storing a 128-bit AdvSIMD register"
   (and (match_code "mem")
@@ -336,32 +336,32 @@
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1rq_operand_p (op)")))
 
-(define_memory_constraint "UOb"
+(define_relaxed_memory_constraint "UOb"
   "@internal
    An address valid for SVE LD1ROH."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)")))
 
-(define_memory_constraint "UOh"
+(define_relaxed_memory_constraint "UOh"
   "@internal
    An address valid for SVE LD1ROH."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)")))
 
 
-(define_memory_constraint "UOw"
+(define_relaxed_memory_constraint "UOw"
   "@internal
    An address valid for SVE LD1ROW."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)")))
 
-(define_memory_constraint "UOd"
+(define_relaxed_memory_constraint "UOd"
   "@internal
    An address valid for SVE LD1ROD."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)")))
 
-(define_memory_constraint "Uty"
+(define_relaxed_memory_constraint "Uty"
   "@internal
    An address valid for SVE LD1Rs."
   (and (match_code "mem")