diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b55cb58078d..a3f68ad9c1a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -32450,6 +32450,9 @@
 (define_mode_attr ssebvecmode_2
   [(V8HF "V16QI") (V16HF "V16QI") (V32HF "V32QI")])
 
+(define_mode_attr iptrssebvec_2
+  [(V8HF "q") (V16HF "") (V32HF "")])
+
 (define_int_iterator UNSPEC_VCVTBIASPH2FP8_PACK
    [UNSPEC_VCVTBIASPH2BF8 UNSPEC_VCVTBIASPH2BF8S
     UNSPEC_VCVTBIASPH2HF8 UNSPEC_VCVTBIASPH2HF8S])
@@ -32626,7 +32629,7 @@
 	  [(match_operand:<ssebvecmode_2> 1 "nonimmediate_operand" "vm")]
 	  UNSPEC_VCVTHF82PH))]
   "TARGET_AVX10_2"
-  "vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  "vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptrssebvec_2>1}"
   [(set_attr "prefix" "evex")])
 
 (define_int_iterator VPDPWPROD
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-pr124349-2.c b/gcc/testsuite/gcc.target/i386/avx10_2-pr124349-2.c
new file mode 100644
index 00000000000..901559794ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-pr124349-2.c
@@ -0,0 +1,41 @@
+/* PR target/124349 */
+/* { dg-do assemble { target { avx10_2 && masm_intel } } } */
+/* { dg-options "-O2 -mavx10.2 -masm=intel" } */
+
+#include <x86intrin.h>
+
+__m128h
+foo (__m128i *p)
+{
+  return _mm_cvthf8_ph (*p);
+}
+
+__m128h
+bar (__m128i *p, __m128h w, __mmask8 u)
+{
+  return _mm_mask_cvthf8_ph (w, u, *p);
+}
+
+__m256h
+baz (__m128i *p)
+{
+  return _mm256_cvthf8_ph (*p);
+}
+
+__m256h
+qux (__m128i *p, __m256h w, __mmask16 u)
+{
+  return _mm256_mask_cvthf8_ph (w, u, *p);
+}
+
+__m512h
+fred (__m256i *p)
+{
+  return _mm512_cvthf8_ph (*p);
+}
+
+__m512h
+corge (__m256i *p, __m512h w, __mmask32 u)
+{
+  return _mm512_mask_cvthf8_ph (w, u, *p);
+}