J. Neuschäfer b1ad45acdd Fix memory barriers on ARMv5 ...

The ARM926EJ-S Technical Reference Manual states:

> You can only access CP15 registers with MRC and MCR instructions in a
> privileged mode. CDP, LDC, STC, MCRR, and MRRC instructions, and unprivileged
> MRC or MCR instructions to CP15 cause the Undefined instruction exception to
> be taken.

Furthermore, `MCR p15, 0, <Rd>, c7, c10, 5` (later called Data Memory Barrier)
is not specified for the ARM926. Thus, SDL should not use these cache
instructions on ARMv5.

(cherry picked from commit 139a0931a3)

2024-01-05 09:01:30 -08:00

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