TeamHeptaMirrors/gcc
1
0
Fork 1
mirror of https://github.com/gcc-mirror/gcc.git synced 2026-05-06 14:59:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

RISC-V: Fix scalar code-gen of unsigned SAT_MUL

Browse Source 
The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
Leverage the mulhs by mistake, it should be mulhu for the
hight bit result of mul.  Thus, this patch would like to make
it correct.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take
	umulhu for high bits mul result.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c: Add mulhu
	asm check.
	* gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li
2025-07-31 12:32:24 +08:00
parent aa558046c0
commit 01a784e7c5
3 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
gcc/config/riscv/riscv.cc
View File

@@ -13867,9 +13867,9 @@ riscv_expand_xmode_usmul (rtx dest, rtx x, rtx y)
riscv_emit_binary (MULT, mul, x, y);
if (TARGET_64BIT)
emit_insn (gen_usmuldi3_highpart (mulhu, x, y));
emit_insn (gen_umuldi3_highpart (mulhu, x, y));
else
emit_insn (gen_usmulsi3_highpart (mulhu, x, y));
emit_insn (gen_umulsi3_highpart (mulhu, x, y));
riscv_emit_binary (NE, overflow_p, mulhu, CONST0_RTX (Xmode));
riscv_emit_unary (NEG, overflow_p, overflow_p);

2
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c
View File

@@ -9,3 +9,5 @@
DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT)
/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */
/* { dg-final { scan-assembler-times "mulhu" 1 } } */

1
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c
View File

@@ -10,3 +10,4 @@ DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT)
/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */
/* { dg-final { scan-assembler-times "mulhu" 1 } } */