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RISC-V: Reconcile the existing test for vdivu.vx combine

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Some existing vdiv related test need some adjust for the
asm check due to cost model.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adjust
	the asm check for vdivu.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li
2025-06-06 10:03:50 +08:00
parent c01830fa80
commit 08a0b6dabd
4 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
View File

@@ -5,8 +5,8 @@
/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */
/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
View File

@@ -5,8 +5,8 @@
/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
/* Division by constant is done by calculating a reciprocal and
then multiplying. Hence we do not expect 6 vfdivs. */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
View File

@@ -5,8 +5,8 @@
/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */
/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
View File

@@ -5,8 +5,8 @@
/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */
/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */
/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */
/* Division by constant is done by calculating a reciprocal and
then multiplying. Hence we do not expect 6 vfdivs. */