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RISC-V: Add another combine pattern for vfmin/max on cost model

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The recent change introduce another form of vfmin/max, which is
more "literal" compare the previous one.  The related vx_vf/vf*
test cases also failed due to this change.  Thus, add the pattern
to make the test case happy.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
* Fix the vx_vf/vf* testcases.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*literal_v<ieee_fmaxmin_op>_vf_<mode>):
	Add new pattern for vfmax/min combine to fx.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li
2026-02-17 19:15:36 +08:00
parent ff2f6c5153
commit 63fc48f077
1 changed files with 28 additions and 0 deletions
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28
gcc/config/riscv/autovec-opt.md
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@@ -2244,6 +2244,34 @@
[(set_attr "type" "vfminmax")]
)
(define_insn_and_split "*literal_v<ieee_fmaxmin_op>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 5 "vector_length_operand")
(match_operand 6 "const_int_operand")
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:V_VLSF
[(vec_duplicate:V_VLSF
(match_operand:<VEL> 3 "register_operand"))
(match_operand:V_VLSF 4 "register_operand")] UNSPEC_VFMAXMIN)
(unspec:V_VLSF
[(match_operand:DI 2 "register_operand")] UNSPEC_VUNDEF)))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
rtx ops[] = {operands[0], operands[4], operands[3]};
insn_code icode = code_for_pred_scalar (<IEEE_FMAXMIN_OP>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, ops);
}
[(set_attr "type" "vfminmax")])
(define_insn_and_split "*v<ieee_fmaxmin_op>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
(unspec:V_VLSF [