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arm: testsuite: [MVE] Fix expected code for vadcq_m and vsbcq_m [PR122189]

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The original versions of these tests only took into account code
generated with -mfloat-abi=hard.

Depending on how the toolchain is configured, arm_v8_1m_mve may use
-mfloat-abi-softfp, which generates a different instructions order.

Depending on the -mtune setting, the order can also vary, so the patch
adds -fno-schedule-insns -fno-schedule-insns2 to avoid such
maintenance issues.

In particular, this fixes the failures with:
 -mthumb -march=armv7e-m+fp.dp -mtune=cortex-m7 -mfloat-abi=hard -mfpu=auto
 -mthumb -march=armv6s-m -mtune=cortex-m0 -mfloat-abi=soft -mfpu=auto

gcc/testsuite/ChangeLog:

	PR target/122189
	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
This commit is contained in:
Christophe Lyon
2025-10-20 14:31:21 +00:00
parent 80af807e52
commit 697ccadd72
4 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
View File

@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)

10
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
View File

@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)

10
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
View File

@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)

10
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
View File

@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)