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Fix revision 193651.
gcc/ * config/aarch64/atomics.md: Actually add this file. From-SVN: r193653
This commit is contained in:
James Greenhalgh
382
gcc/config/aarch64/atomics.md
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382
gcc/config/aarch64/atomics.md
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@@ -0,0 +1,382 @@
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;; Machine description for AArch64 processor synchronization primitives.
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;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
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;; Contributed by ARM Ltd.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_c_enum "unspecv"
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[
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UNSPECV_LX ; Represent a load-exclusive.
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UNSPECV_SX ; Represent a store-exclusive.
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UNSPECV_LDA ; Represent an atomic load or load-acquire.
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UNSPECV_STL ; Represent an atomic store or store-release.
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UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
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UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
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UNSPECV_ATOMIC_OP ; Represent an atomic operation.
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])
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(define_expand "atomic_compare_and_swap<mode>"
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[(match_operand:SI 0 "register_operand" "") ;; bool out
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(match_operand:ALLI 1 "register_operand" "") ;; val out
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(match_operand:ALLI 2 "aarch64_sync_memory_operand" "") ;; memory
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(match_operand:ALLI 3 "general_operand" "") ;; expected
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(match_operand:ALLI 4 "register_operand" "") ;; desired
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(match_operand:SI 5 "const_int_operand") ;; is_weak
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(match_operand:SI 6 "const_int_operand") ;; mod_s
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(match_operand:SI 7 "const_int_operand")] ;; mod_f
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""
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{
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aarch64_expand_compare_and_swap (operands);
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DONE;
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}
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)
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(define_insn_and_split "atomic_compare_and_swap<mode>_1"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(zero_extend:SI
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
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(set (match_dup 1)
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(unspec_volatile:SHORT
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[(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected
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(match_operand:SHORT 3 "register_operand" "r") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))
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(clobber (match_scratch:SI 7 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_compare_and_swap (operands);
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DONE;
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}
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)
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(define_insn_and_split "atomic_compare_and_swap<mode>_1"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:GPI 0 "register_operand" "=&r") ;; val out
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect
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(match_operand:GPI 3 "register_operand" "r") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))
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(clobber (match_scratch:SI 7 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_compare_and_swap (operands);
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DONE;
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}
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)
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(define_insn_and_split "atomic_exchange<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r") ;; output
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:ALLI
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[(match_operand:ALLI 2 "register_operand" "r") ;; input
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(match_operand:SI 3 "const_int_operand" "")] ;; model
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UNSPECV_ATOMIC_EXCHG))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:SI 4 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
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operands[2], operands[3], operands[4]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_<atomic_optab><mode>"
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[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
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(unspec_volatile:ALLI
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[(atomic_op:ALLI (match_dup 0)
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(match_operand:ALLI 1 "<atomic_op_operand>" "rn"))
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:ALLI 3 "=&r"))
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(clobber (match_scratch:SI 4 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_atomic_op (<CODE>, NULL, operands[3], operands[0],
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operands[1], operands[2], operands[4]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_nand<mode>"
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[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
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(unspec_volatile:ALLI
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[(not:ALLI
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(and:ALLI (match_dup 0)
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(match_operand:ALLI 1 "aarch64_logical_operand" "rn")))
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:ALLI 3 "=&r"))
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(clobber (match_scratch:SI 4 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
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operands[1], operands[2], operands[4]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_fetch_<atomic_optab><mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
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(set (match_dup 1)
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(unspec_volatile:ALLI
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[(atomic_op:ALLI (match_dup 1)
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(match_operand:ALLI 2 "<atomic_op_operand>" "rn"))
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:ALLI 4 "=&r"))
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(clobber (match_scratch:SI 5 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_atomic_op (<CODE>, operands[0], operands[4], operands[1],
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operands[2], operands[3], operands[5]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_fetch_nand<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q"))
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(set (match_dup 1)
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(unspec_volatile:ALLI
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[(not:ALLI
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(and:ALLI (match_dup 1)
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(match_operand:ALLI 2 "aarch64_logical_operand" "rn")))
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:ALLI 4 "=&r"))
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(clobber (match_scratch:SI 5 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
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operands[2], operands[3], operands[5]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_<atomic_optab>_fetch<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(atomic_op:ALLI
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")
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(match_operand:ALLI 2 "<atomic_op_operand>" "rn")))
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(set (match_dup 1)
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(unspec_volatile:ALLI
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[(match_dup 1) (match_dup 2)
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:SI 4 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_atomic_op (<CODE>, NULL, operands[0], operands[1],
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operands[2], operands[3], operands[4]);
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DONE;
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}
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)
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(define_insn_and_split "atomic_nand_fetch<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=&r")
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(not:ALLI
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(and:ALLI
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")
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(match_operand:ALLI 2 "aarch64_logical_operand" "rn"))))
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(set (match_dup 1)
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(unspec_volatile:ALLI
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[(match_dup 1) (match_dup 2)
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPECV_ATOMIC_OP))
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(clobber (reg:CC CC_REGNUM))
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(clobber (match_scratch:SI 4 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
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operands[2], operands[3], operands[4]);
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DONE;
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}
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)
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(define_insn "atomic_load<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=r")
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(unspec_volatile:ALLI
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[(match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q")
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPECV_LDA))]
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""
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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if (model == MEMMODEL_RELAXED
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|| model == MEMMODEL_CONSUME
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|| model == MEMMODEL_RELEASE)
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return "ldr<atomic_sfx>\t%<w>0, %1";
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else
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return "ldar<atomic_sfx>\t%<w>0, %1";
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}
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)
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(define_insn "atomic_store<mode>"
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[(set (match_operand:ALLI 0 "memory_operand" "=Q")
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(unspec_volatile:ALLI
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[(match_operand:ALLI 1 "general_operand" "rZ")
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPECV_STL))]
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""
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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if (model == MEMMODEL_RELAXED
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|| model == MEMMODEL_CONSUME
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|| model == MEMMODEL_ACQUIRE)
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return "str<atomic_sfx>\t%<w>1, %0";
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else
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return "stlr<atomic_sfx>\t%<w>1, %0";
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}
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)
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(define_insn "aarch64_load_exclusive<mode>"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI
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(unspec_volatile:SHORT
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[(match_operand:SHORT 1 "aarch64_sync_memory_operand" "Q")
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(match_operand:SI 2 "const_int_operand")]
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UNSPECV_LX)))]
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""
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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if (model == MEMMODEL_RELAXED
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|| model == MEMMODEL_CONSUME
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|| model == MEMMODEL_RELEASE)
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return "ldxr<atomic_sfx>\t%w0, %1";
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else
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return "ldaxr<atomic_sfx>\t%w0, %1";
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}
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)
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(define_insn "aarch64_load_exclusive<mode>"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(unspec_volatile:GPI
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[(match_operand:GPI 1 "aarch64_sync_memory_operand" "Q")
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(match_operand:SI 2 "const_int_operand")]
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UNSPECV_LX))]
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""
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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if (model == MEMMODEL_RELAXED
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|| model == MEMMODEL_CONSUME
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|| model == MEMMODEL_RELEASE)
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return "ldxr\t%<w>0, %1";
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else
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return "ldaxr\t%<w>0, %1";
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}
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)
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(define_insn "aarch64_store_exclusive<mode>"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec_volatile:SI [(const_int 0)] UNSPECV_SX))
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(set (match_operand:ALLI 1 "aarch64_sync_memory_operand" "=Q")
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(unspec_volatile:ALLI
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[(match_operand:ALLI 2 "register_operand" "r")
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(match_operand:SI 3 "const_int_operand")]
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UNSPECV_SX))]
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""
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[3]);
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if (model == MEMMODEL_RELAXED
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|| model == MEMMODEL_CONSUME
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|| model == MEMMODEL_ACQUIRE)
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return "stxr<atomic_sfx>\t%w0, %<w>2, %1";
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else
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return "stlxr<atomic_sfx>\t%w0, %<w>2, %1";
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}
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)
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(define_expand "mem_thread_fence"
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[(match_operand:SI 0 "const_int_operand" "")]
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""
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[0]);
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if (model != MEMMODEL_RELAXED && model != MEMMODEL_CONSUME)
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emit_insn (gen_dmb (operands[0]));
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DONE;
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}
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)
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(define_expand "dmb"
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[(set (match_dup 1)
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(unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
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UNSPEC_MB))]
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""
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{
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operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[1]) = 1;
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}
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)
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(define_insn "*dmb"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
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UNSPEC_MB))]
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""
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{
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enum memmodel model = (enum memmodel) INTVAL (operands[1]);
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if (model == MEMMODEL_ACQUIRE)
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return "dmb\\tishld";
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else
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return "dmb\\tish";
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}
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)
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