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This patch adds support to vectorize sum of abslolute differences (SAD_EXPR)
using SVE.
Given this input code:
int
sum_abs (uint8_t *restrict x, uint8_t *restrict y, int n)
{
int sum = 0;
for (int i = 0; i < n; i++)
{
sum += __builtin_abs (x[i] - y[i]);
}
return sum;
}
The resulting SVE code is:
0000000000000000 <sum_abs>:
0: 7100005f cmp w2, #0x0
4: 5400026d b.le 50 <sum_abs+0x50>
8: d2800003 mov x3, #0x0 // #0
c: 93407c42 sxtw x2, w2
10: 2538c002 mov z2.b, #0
14: 25221fe0 whilelo p0.b, xzr, x2
18: 2538c023 mov z3.b, #1
1c: 2518e3e1 ptrue p1.b
20: a4034000 ld1b {z0.b}, p0/z, [x0, x3]
24: a4034021 ld1b {z1.b}, p0/z, [x1, x3]
28: 0430e3e3 incb x3
2c: 0520c021 sel z1.b, p0, z1.b, z0.b
30: 25221c60 whilelo p0.b, x3, x2
34: 040d0420 uabd z0.b, p1/m, z0.b, z1.b
38: 44830402 udot z2.s, z0.b, z3.b
3c: 54ffff21 b.ne 20 <sum_abs+0x20> // b.any
40: 2598e3e0 ptrue p0.s
44: 04812042 uaddv d2, p0, z2.s
48: 1e260040 fmov w0, s2
4c: d65f03c0 ret
50: 1e2703e2 fmov s2, wzr
54: 1e260040 fmov w0, s2
58: d65f03c0 ret
Notice how udot is used inside a fully masked loop.
gcc/Changelog:
2019-05-07 Alejandro Martinez <alejandro.martinezvicente@arm.com>
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): New define_expand.
(aarch64_<su>abd<mode>_3): Likewise.
(*aarch64_<su>abd<mode>_3): New define_insn.
(<sur>sad<vsi2qi>): New define_expand.
* config/aarch64/iterators.md: Added MAX_OPP attribute.
* tree-vect-loop.c (use_mask_by_cond_expr_p): Add SAD_EXPR.
(build_vect_cond_expr): Likewise.
gcc/testsuite/Changelog:
2019-05-07 Alejandro Martinez <alejandro.martinezvicente@arm.com>
* gcc.target/aarch64/sve/sad_1.c: New test for sum of absolute
differences.
From-SVN: r270975
This commit is contained in:
Alejandro Martinez
committed by
Alejandro Martinez
Alejandro Martinez
parent
0a59215131
commit
a9fad8fe6c
@@ -1,3 +1,13 @@
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2019-05-07 Alejandro Martinez <alejandro.martinezvicente@arm.com>
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* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): New define_expand.
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(aarch64_<su>abd<mode>_3): Likewise.
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(*aarch64_<su>abd<mode>_3): New define_insn.
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(<sur>sad<vsi2qi>): New define_expand.
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* config/aarch64/iterators.md: Added MAX_OPP attribute.
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* tree-vect-loop.c (use_mask_by_cond_expr_p): Add SAD_EXPR.
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(build_vect_cond_expr): Likewise.
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2019-05-07 Uroš Bizjak <ubizjak@gmail.com>
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* cfgexpand.c (asm_clobber_reg_is_valid): Reject
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@@ -3148,3 +3148,64 @@
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movprfx\t%0, %3\;<sur>dot\\t%0.<Vetype>, %1.<Vetype_fourth>, %2.<Vetype_fourth>"
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[(set_attr "movprfx" "*,yes")]
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)
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;; Helper expander for aarch64_<su>abd<mode>_3 to save the callers
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;; the hassle of constructing the other arm of the MINUS.
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(define_expand "<su>abd<mode>_3"
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[(use (match_operand:SVE_I 0 "register_operand"))
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(USMAX:SVE_I (match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "register_operand"))]
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"TARGET_SVE"
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{
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rtx pred = force_reg (<VPRED>mode, CONSTM1_RTX (<VPRED>mode));
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rtx other_arm = gen_rtx_<MAX_OPP> (<MODE>mode, operands[1], operands[2]);
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emit_insn (gen_aarch64_<su>abd<mode>_3 (operands[0], pred, operands[1],
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operands[2], other_arm));
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DONE;
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}
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)
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;; Predicated integer absolute difference.
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(define_insn "aarch64_<su>abd<mode>_3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(minus:SVE_I
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(USMAX:SVE_I
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(match_operand:SVE_I 2 "register_operand" "0, w")
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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(match_operator 4 "aarch64_<max_opp>"
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[(match_dup 2)
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(match_dup 3)]))]
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UNSPEC_MERGE_PTRUE))]
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"TARGET_SVE"
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"@
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<su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0, %2\;<su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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[(set_attr "movprfx" "*,yes")]
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)
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;; Emit a sequence to produce a sum-of-absolute-differences of the inputs in
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;; operands 1 and 2. The sequence also has to perform a widening reduction of
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;; the difference into a vector and accumulate that into operand 3 before
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;; copying that into the result operand 0.
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;; Perform that with a sequence of:
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;; MOV ones.b, #1
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;; [SU]ABD diff.b, p0/m, op1.b, op2.b
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;; MOVPRFX op0, op3 // If necessary
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;; UDOT op0.s, diff.b, ones.b
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(define_expand "<sur>sad<vsi2qi>"
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[(use (match_operand:SVE_SDI 0 "register_operand"))
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(unspec:<VSI2QI> [(use (match_operand:<VSI2QI> 1 "register_operand"))
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(use (match_operand:<VSI2QI> 2 "register_operand"))] ABAL)
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(use (match_operand:SVE_SDI 3 "register_operand"))]
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"TARGET_SVE"
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{
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rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
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rtx diff = gen_reg_rtx (<VSI2QI>mode);
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emit_insn (gen_<sur>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
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emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
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DONE;
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}
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)
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@@ -1060,6 +1060,9 @@
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;; Map smax to smin and umax to umin.
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(define_code_attr max_opp [(smax "smin") (umax "umin")])
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;; Same as above, but louder.
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(define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
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;; The number of subvectors in an SVE_STRUCT.
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(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
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(VNx8SI "2") (VNx4DI "2")
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@@ -1,3 +1,8 @@
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2019-05-07 Alejandro Martinez <alejandro.martinezvicente@arm.com>
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* gcc.target/aarch64/sve/sad_1.c: New test for sum of absolute
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differences.
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2019-05-07 Uroš Bizjak <ubizjak@gmail.com>
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* gcc.target/i386/asm-7.c: New test.
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28
gcc/testsuite/gcc.target/aarch64/sve/sad_1.c
Normal file
28
gcc/testsuite/gcc.target/aarch64/sve/sad_1.c
Normal file
@@ -0,0 +1,28 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define DEF_SAD(TYPE1, TYPE2) \
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TYPE1 __attribute__ ((noinline, noclone)) \
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sum_abs_##TYPE1##_##TYPE2 (TYPE2 *restrict x, TYPE2 *restrict y, int n) \
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{ \
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TYPE1 sum = 0; \
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for (int i = 0; i < n; i++) \
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{ \
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sum += __builtin_abs (x[i] - y[i]); \
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} \
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return sum; \
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}
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DEF_SAD(int32_t, uint8_t)
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DEF_SAD(int32_t, int8_t)
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DEF_SAD(int64_t, uint16_t)
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DEF_SAD(int64_t, int16_t)
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/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tudot\tz[0-9]+\.s, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tuabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tudot\tz[0-9]+\.d, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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@@ -5973,6 +5973,7 @@ use_mask_by_cond_expr_p (enum tree_code code, internal_fn cond_fn,
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switch (code)
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{
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case DOT_PROD_EXPR:
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case SAD_EXPR:
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return true;
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default:
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@@ -6002,6 +6003,17 @@ build_vect_cond_expr (enum tree_code code, tree vop[3], tree mask,
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break;
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}
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case SAD_EXPR:
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{
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tree vectype = TREE_TYPE (vop[1]);
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tree masked_op1 = make_temp_ssa_name (vectype, NULL, "masked_op1");
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gassign *select = gimple_build_assign (masked_op1, VEC_COND_EXPR,
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mask, vop[1], vop[0]);
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gsi_insert_before (gsi, select, GSI_SAME_STMT);
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vop[1] = masked_op1;
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break;
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}
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default:
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gcc_unreachable ();
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}
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