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mips-protos.h (mips_reg_mode_ok_for_base_p): Delete.
* config/mips/mips-protos.h (mips_reg_mode_ok_for_base_p): Delete. (mips_regno_mode_ok_for_base_p): Declare. * config/mips/mips.h (ARG_POINTER_REGNUM): Renumber to 77. (FRAME_POINTER_REGNUM): Renumber to 78. (FIRST_PSEUDO_REGISTER): Update comment accordingly. (BASE_REG_P, GP_REG_OR_PSEUDO_STRICT_P): Delete. (GP_REG_OR_PSEUDO_NONSTRICT_P): Delete. (REGNO_MODE_OK_FOR_BASE_P): Use mips_regno_mode_ok_for_base_p. (REG_MODE_OK_FOR_BASE_P): Likewise. * config/mips/mips.c (mips_reg_names, mips_sw_reg_names): Change entry for 77 to "$arg" and entry for 78 to "$frame". (mips_regno_to_class): Map 77 and 78 to ALL_REGS. (mips_reg_mode_ok_for_base_p): Remove. (mips_regno_mode_ok_for_base_p): New function, derived from old BASE_REG_P macro. Don't enforce the mips16 stack pointer restrictions unless we're being strict. (mips_valid_base_register_p): Use mips_regno_mode_ok_for_base_p. testsuite/ * gcc.dg/torture/mips-clobber-at.c: New test. From-SVN: r76547
This commit is contained in:
Richard Sandiford
committed by
Richard Sandiford
Richard Sandiford
parent
0ce78f010d
commit
bcbc6b7fb8
@@ -1,3 +1,23 @@
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2004-01-25 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips-protos.h (mips_reg_mode_ok_for_base_p): Delete.
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(mips_regno_mode_ok_for_base_p): Declare.
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* config/mips/mips.h (ARG_POINTER_REGNUM): Renumber to 77.
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(FRAME_POINTER_REGNUM): Renumber to 78.
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(FIRST_PSEUDO_REGISTER): Update comment accordingly.
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(BASE_REG_P, GP_REG_OR_PSEUDO_STRICT_P): Delete.
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(GP_REG_OR_PSEUDO_NONSTRICT_P): Delete.
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(REGNO_MODE_OK_FOR_BASE_P): Use mips_regno_mode_ok_for_base_p.
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(REG_MODE_OK_FOR_BASE_P): Likewise.
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* config/mips/mips.c (mips_reg_names, mips_sw_reg_names): Change
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entry for 77 to "$arg" and entry for 78 to "$frame".
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(mips_regno_to_class): Map 77 and 78 to ALL_REGS.
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(mips_reg_mode_ok_for_base_p): Remove.
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(mips_regno_mode_ok_for_base_p): New function, derived from old
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BASE_REG_P macro. Don't enforce the mips16 stack pointer
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restrictions unless we're being strict.
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(mips_valid_base_register_p): Use mips_regno_mode_ok_for_base_p.
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2004-01-24 Kazu Hirata <kazu@cs.umass.edu>
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* c-common.h: Fix comment typos.
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@@ -26,7 +26,7 @@ Boston, MA 02111-1307, USA. */
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#ifndef GCC_MIPS_PROTOS_H
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#define GCC_MIPS_PROTOS_H
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extern int mips_reg_mode_ok_for_base_p (rtx, enum machine_mode, int);
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extern int mips_regno_mode_ok_for_base_p (int, enum machine_mode, int);
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extern int mips_address_insns (rtx, enum machine_mode);
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extern int mips_const_insns (rtx);
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extern int mips_fetch_insns (rtx);
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@@ -572,7 +572,7 @@ char mips_reg_names[][8] =
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"$fcc5","$fcc6","$fcc7","", "", "", "", "$fakec",
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"$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",
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"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
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"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
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"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
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@@ -601,7 +601,7 @@ char mips_sw_reg_names[][8] =
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"$fcc5","$fcc6","$fcc7","$rap", "", "", "", "$fakec",
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"$fcc5","$fcc6","$fcc7","$rap", "", "$arg", "$frame", "$fakec",
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"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
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"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
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"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
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@@ -638,7 +638,7 @@ const enum reg_class mips_regno_to_class[] =
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HI_REG, LO_REG, NO_REGS, ST_REGS,
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ST_REGS, ST_REGS, ST_REGS, ST_REGS,
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ST_REGS, ST_REGS, ST_REGS, NO_REGS,
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NO_REGS, NO_REGS, NO_REGS, NO_REGS,
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NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
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COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
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COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
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COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
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@@ -953,11 +953,40 @@ mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
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/* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
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int
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mips_reg_mode_ok_for_base_p (rtx reg, enum machine_mode mode, int strict)
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mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
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{
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return (strict
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? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
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: GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
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if (regno >= FIRST_PSEUDO_REGISTER)
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{
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if (!strict)
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return true;
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regno = reg_renumber[regno];
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}
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/* These fake registers will be eliminated to either the stack or
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hard frame pointer, both of which are usually valid base registers.
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Reload deals with the cases where the eliminated form isn't valid. */
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if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
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return true;
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/* In mips16 mode, the stack pointer can only address word and doubleword
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values, nothing smaller. There are two problems here:
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(a) Instantiating virtual registers can introduce new uses of the
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stack pointer. If these virtual registers are valid addresses,
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the stack pointer should be too.
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(b) Most uses of the stack pointer are not made explicit until
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FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
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We don't know until that stage whether we'll be eliminating to the
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stack pointer (which needs the restriction) or the hard frame
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pointer (which doesn't).
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All in all, it seems more consitent to only enforce this restriction
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during and after reload. */
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if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
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return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
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return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
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}
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@@ -971,7 +1000,7 @@ mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
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x = SUBREG_REG (x);
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return (GET_CODE (x) == REG
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&& mips_reg_mode_ok_for_base_p (x, mode, strict));
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&& mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
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}
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@@ -1474,8 +1474,11 @@ extern const struct mips_cpu_info *mips_tune_info;
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- 8 condition code registers
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- 2 accumulator registers (hi and lo)
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- 32 registers each for coprocessors 0, 2 and 3
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- FAKE_CALL_REGNO (see the comment above load_callsi for details)
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- 5 dummy entries that were used at various times in the past. */
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- 3 fake registers:
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- ARG_POINTER_REGNUM
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- FRAME_POINTER_REGNUM
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- FAKE_CALL_REGNO (see the comment above load_callsi for details)
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- 3 dummy entries that were used at various times in the past. */
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#define FIRST_PSEUDO_REGISTER 176
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@@ -1661,11 +1664,10 @@ extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
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/* Base register for access to local variables of the function. We
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pretend that the frame pointer is $1, and then eliminate it to
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HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
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a fixed register, and will not be used for anything else. */
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#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
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/* These two registers don't really exist: they get eliminated to either
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the stack or hard frame pointer. */
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#define ARG_POINTER_REGNUM 77
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#define FRAME_POINTER_REGNUM 78
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/* $30 is not available on the mips16, so we use $17 as the frame
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pointer. */
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@@ -1678,9 +1680,6 @@ extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
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This is computed in `reload', in reload1.c. */
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#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM GP_REG_FIRST
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/* Register in which static-chain is passed to a function. */
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#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
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@@ -2510,31 +2509,9 @@ typedef struct mips_args {
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/* Addressing modes, and classification of registers for them. */
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/* These assume that REGNO is a hard or pseudo reg number.
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They give nonzero only if REGNO is a hard reg of the suitable class
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or a pseudo reg currently allocated to a suitable hard reg.
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These definitions are NOT overridden anywhere. */
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#define BASE_REG_P(regno, mode) \
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(TARGET_MIPS16 \
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? (M16_REG_P (regno) \
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|| (regno) == FRAME_POINTER_REGNUM \
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|| (regno) == ARG_POINTER_REGNUM \
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|| ((regno) == STACK_POINTER_REGNUM \
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&& (GET_MODE_SIZE (mode) == 4 \
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|| GET_MODE_SIZE (mode) == 8))) \
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: GP_REG_P (regno))
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#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
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BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
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(mode))
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#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
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(((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
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#define REGNO_OK_FOR_INDEX_P(regno) 0
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#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
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GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
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#define REGNO_OK_FOR_INDEX_P(REGNO) 0
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#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
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mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
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/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
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and check its validity for a certain class.
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@@ -2549,10 +2526,10 @@ typedef struct mips_args {
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#ifndef REG_OK_STRICT
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#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
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mips_reg_mode_ok_for_base_p (X, MODE, 0)
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mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
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#else
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#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
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mips_reg_mode_ok_for_base_p (X, MODE, 1)
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mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
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#endif
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#define REG_OK_FOR_INDEX_P(X) 0
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@@ -1,3 +1,7 @@
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2004-01-25 Richard Sandiford <rsandifo@redhat.com>
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* gcc.dg/torture/mips-clobber-at.c: New test.
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2004-01-24 Ian Lance Taylor <ian@wasabisystems.com>
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* gcc.dg/20040124-1.c: New test.
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4
gcc/testsuite/gcc.dg/torture/mips-clobber-at.c
Normal file
4
gcc/testsuite/gcc.dg/torture/mips-clobber-at.c
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@@ -0,0 +1,4 @@
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/* "$1" used to be mapped to the internal frame pointer. */
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/* { dg-do compile { target mips*-*-* } } */
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/* { dg-options "" } */
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int foo () { asm volatile ("#" ::: "$1"); }
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