TeamHeptaMirrors/gcc
1
0
Fork 1
mirror of https://github.com/gcc-mirror/gcc.git synced 2026-05-06 14:59:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

arm: [MVE intrinsics] factorize vmaxq vminq

Browse Source 
Factorize vmaxq and vminq so that they use the same pattern.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MAX_MIN_SU): New.
	(max_min_su_str): New.
	(max_min_supf): New.
	* config/arm/mve.md (mve_vmaxq_s<mode>, mve_vmaxq_u<mode>)
	(mve_vminq_s<mode>, mve_vminq_u<mode>): Merge into ...
	(mve_<max_min_su_str>q_<max_min_supf><mode>): ... this.
This commit is contained in:
Christophe Lyon
2022-10-24 14:01:51 +00:00
parent 9e838ad14b
commit bcf66a4dcb
2 changed files with 16 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
gcc/config/arm/iterators.md
View File

@@ -330,6 +330,9 @@
;; Saturating addition, subtraction
(define_code_iterator SSPLUSMINUS [ss_plus ss_minus])
;; Max/Min iterator, to factorize MVE patterns
(define_code_iterator MAX_MIN_SU [smax umax smin umin])
;; MVE integer binary operations.
(define_code_iterator MVE_INT_BINARY_RTX [plus minus mult])
@@ -1271,6 +1274,14 @@
(define_code_attr float_SUP [(unsigned_float "U") (float "S")])
;; max/min for MVE
(define_code_attr max_min_su_str [(smax "vmax") (umax "vmax") (smin "vmin") (umin "vmin")])
(define_code_attr max_min_supf [
(smax "s") (umax "u")
(smin "s") (umin "u")
])
;;----------------------------------------------------------------------------
;; Int attributes
;;----------------------------------------------------------------------------

44
gcc/config/arm/mve.md
View File

@@ -1106,29 +1106,20 @@
])
;;
;; [vmaxq_u, vmaxq_s])
;; [vmaxq_u, vmaxq_s]
;; [vminq_s, vminq_u]
;;
(define_insn "mve_vmaxq_s<mode>"
(define_insn "mve_<max_min_su_str>q_<max_min_supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(smax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
(MAX_MIN_SU:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
"vmax.%#<V_s_elem>\t%q0, %q1, %q2"
"<max_min_su_str>.<max_min_supf>%#<V_sz_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
(define_insn "mve_vmaxq_u<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(umax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
"vmax.%#<V_u_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vmaxvq_u, vmaxvq_s])
@@ -1175,31 +1166,6 @@
[(set_attr "type" "mve_move")
])
;;
;; [vminq_s, vminq_u])
;;
(define_insn "mve_vminq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(smin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
"vmin.%#<V_s_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
(define_insn "mve_vminq_u<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(umin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
"vmin.%#<V_u_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vminvq_u, vminvq_s])
;;