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Daily bump.
This commit is contained in:
GCC Administrator
@@ -1,3 +1,102 @@
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2023-05-02 Andrew Pinski <apinski@marvell.com>
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* tree-ssa-phiopt.cc (move_stmt): New function.
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(match_simplify_replacement): Use move_stmt instead
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of the inlined version.
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2023-05-02 Andrew Pinski <apinski@marvell.com>
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* match.pd (a != 0 ? CLRSB(a) : CST -> CLRSB(a)): New
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pattern.
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2023-05-02 Andrew Pinski <apinski@marvell.com>
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PR tree-optimization/109702
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* match.pd: Fix "a != 0 ? FUNC(a) : CST" patterns
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for FUNC of POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
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2023-05-02 Andrew Pinski <apinski@marvell.com>
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PR target/109657
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* config/aarch64/aarch64.md (*cmov<mode>_insn_m1): New
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insn_and_split pattern.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/sync.md (atomic_load<mode>): Implement atomic
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load mapping.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/sync.md (mem_thread_fence_1): Change fence
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depending on the given memory model.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
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riscv_union_memmodels function to sync.md.
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* config/riscv/riscv.cc (riscv_union_memmodels): Add function to
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get the union of two memmodels in sync.md.
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(riscv_print_operand): Add %I and %J flags that output the
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optimal LR/SC flag bits for a given memory model.
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* config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl
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bits on SC op and replace with optimized %I, %J flags.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/riscv.cc
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(riscv_memmodel_needs_amo_release): Change function name.
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(riscv_print_operand): Remove unneeded %F case.
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* config/riscv/sync.md: Remove unneeded fences.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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PR target/89835
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* config/riscv/sync.md (atomic_store<mode>): Use simple store
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instruction in combination with fence(s).
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/riscv.cc (riscv_print_operand): Change behavior
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of %A to include release bits.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/sync.md (atomic_cas_value_strong<mode>): Change
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FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl
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pair.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
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sequentially consistent LR.aqrl/SC.rl pairs.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
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sanitize memmodel input with memmodel_base.
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2023-05-02 Yanzhang Wang <yanzhang.wang@intel.com>
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Pan Li <pan2.li@intel.com>
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PR target/109617
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* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
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2023-05-02 Romain Naour <romain.naour@gmail.com>
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* config/riscv/genrvv-type-indexer.cc: Use log2 from the C header, without
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the namespace.
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2023-05-02 Martin Liska <mliska@suse.cz>
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* doc/invoke.texi: Update documentation based on param.opt file.
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2023-05-02 Richard Biener <rguenther@suse.de>
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PR tree-optimization/109672
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* tree-vect-stmts.cc (vectorizable_operation): For plus,
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minus and negate always check the vector mode is word mode.
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2023-05-01 Andrew Pinski <apinski@marvell.com>
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* tree-ssa-phiopt.cc: Update comment about
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@@ -1 +1 @@
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20230502
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20230503
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@@ -1,3 +1,28 @@
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2023-05-02 Jason Merrill <jason@redhat.com>
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* pt.cc (instantiate_class_template): Skip the RECORD_TYPE
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of a class template.
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(tsubst_template_decl): Clear CLASSTYPE_USE_TEMPLATE.
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2023-05-02 Jason Merrill <jason@redhat.com>
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* name-lookup.cc (pop_from_top_level): Don't
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invalidate_class_lookup_cache.
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2023-05-02 Jason Merrill <jason@redhat.com>
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PR c++/109678
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* cp-tree.h (lookup_base): Add offset parm.
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* constexpr.cc (cxx_fold_indirect_ref_1): Pass it.
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* search.cc (struct lookup_base_data_s): Add offset.
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(dfs_lookup_base): Handle it.
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(lookup_base): Pass it.
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2023-05-02 Jason Merrill <jason@redhat.com>
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PR c++/109678
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* constexpr.cc (cxx_fold_indirect_ref_1): Handle empty base first.
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2023-05-01 Jason Merrill <jason@redhat.com>
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PR c++/109666
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@@ -1,3 +1,72 @@
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2023-05-02 Andrew Pinski <apinski@marvell.com>
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PR tree-optimization/109702
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* gcc.dg/tree-ssa/phi-opt-25b.c: New test.
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2023-05-02 Andrew Pinski <apinski@marvell.com>
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PR target/109657
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* gcc.target/aarch64/csinv-2.c: New test.
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2023-05-02 Jason Merrill <jason@redhat.com>
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PR c++/109678
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* g++.dg/cpp1z/variant1.C: New test.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test.
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* gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test.
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* gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test.
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* gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test.
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* gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test.
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* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test.
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* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test.
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* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test.
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* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test.
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* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test.
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* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test.
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* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test.
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* gcc.target/riscv/amo-table-a-6-fence-1.c: New test.
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* gcc.target/riscv/amo-table-a-6-fence-2.c: New test.
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* gcc.target/riscv/amo-table-a-6-fence-3.c: New test.
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* gcc.target/riscv/amo-table-a-6-fence-4.c: New test.
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* gcc.target/riscv/amo-table-a-6-fence-5.c: New test.
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* gcc.target/riscv/amo-table-a-6-load-1.c: New test.
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* gcc.target/riscv/amo-table-a-6-load-2.c: New test.
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* gcc.target/riscv/amo-table-a-6-load-3.c: New test.
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* gcc.target/riscv/amo-table-a-6-store-1.c: New test.
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* gcc.target/riscv/amo-table-a-6-store-2.c: New test.
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* gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test.
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* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test.
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* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test.
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* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test.
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* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test.
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* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test.
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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PR target/89835
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* gcc.target/riscv/pr89835.c: New test.
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2023-05-02 Yanzhang Wang <yanzhang.wang@intel.com>
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Pan Li <pan2.li@intel.com>
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PR target/109617
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* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
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2023-05-02 Patrick Palka <ppalka@redhat.com>
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PR c++/109506
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* g++.dg/cpp0x/nsdmi-template26.C: New test.
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2023-05-02 Richard Biener <rguenther@suse.de>
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* gcc.target/i386/pr88531-2a.c: Skip scanning for ia32.
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* gcc.target/i386/pr88531-2b.c: Likewise.
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* gcc.target/i386/pr88531-2c.c: Likewise.
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* gcc.target/i386/pr89618-2.c: Likewise. Disable AVX512.
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2023-05-01 Jason Merrill <jason@redhat.com>
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PR c++/109666
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@@ -1,3 +1,8 @@
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2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
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* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
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sequentially consistent LR.aqrl/SC.rl pairs.
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2023-05-01 Dimitar Dimitrov <dimitar@dinux.eu>
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* config/pru/t-pru (HOST_LIBGCC2_CFLAGS): Add
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@@ -1,3 +1,20 @@
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2023-05-02 Jakub Jelinek <jakub@redhat.com>
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* config/abi/post/aarch64-linux-gnu/baseline_symbols.txt: Update.
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* config/abi/post/i486-linux-gnu/baseline_symbols.txt: Update.
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* config/abi/post/m68k-linux-gnu/baseline_symbols.txt: Update.
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* config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt: Update.
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* config/abi/post/riscv64-linux-gnu/baseline_symbols.txt: Update.
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* config/abi/post/s390x-linux-gnu/baseline_symbols.txt: Update.
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* config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt: Update.
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* config/abi/post/x86_64-linux-gnu/baseline_symbols.txt: Update.
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2023-05-02 Jakub Jelinek <jakub@redhat.com>
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PR libstdc++/109694
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* src/c++98/ios_init.cc: Add #pragma GCC diagnostic ignored for
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-Wattribute-alias.
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2023-04-28 Jonathan Wakely <jwakely@redhat.com>
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* include/bits/random.h (gamma_distribution): Add to the right
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