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nios2: Remove all support for Nios II target.

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nios2 target support in GCC was deprecated in GCC 14 as the
architecture has been EOL'ed by the vendor.  This patch removes the
entire port for GCC 15

There are still references to "nios2" in libffi and libgo.  Since those
libraries are imported into the gcc sources from master copies maintained
by other projects, those will need to be addressed elsewhere.

ChangeLog:
	* MAINTAINERS: Remove references to nios2.
	* configure.ac: Likewise.
	* configure: Regenerated.

config/ChangeLog:
	* mt-nios2-elf: Deleted.

contrib/ChangeLog:
	* config-list.mk: Remove references to Nios II.

gcc/ChangeLog:
	* common/config/nios2/*: Delete entire directory.
	* config/nios2/*: Delete entire directory.
	* config.gcc: Remove references to nios2.
	* configure.ac: Likewise.
	* doc/extend.texi: Likewise.
	* doc/install.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/md.texi: Likewise.
	* regenerate-opt-urls.py: Likewise.
	* config.in: Regenerated.
	* configure: Regenerated.

gcc/testsuite/ChangeLog:
	* g++.target/nios2/*: Delete entire directory.
	* gcc.target/nios2/*: Delete entire directory.
	* g++.dg/cpp0x/constexpr-rom.C: Remove refences to nios2.
	* g++.old-deja/g++.jason/thunk3.C: Likewise.
	* gcc.c-torture/execute/20101011-1.c: Likewise.
	* gcc.c-torture/execute/pr47237.c: Likewise.
	* gcc.dg/20020312-2.c: Likewise.
	* gcc.dg/20021029-1.c: Likewise.
	* gcc.dg/debug/btf/btf-datasec-1.c: Likewise.
	* gcc.dg/ifcvt-4.c: Likewise.
	* gcc.dg/stack-usage-1.c: Likewise.
	* gcc.dg/struct-by-value-1.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
	* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
	* lib/target-supports.exp: Likewise.

libgcc/ChangeLog:
	* config/nios2/*: Delete entire directory.
	* config.host: Remove refences to nios2.
	* unwind-dw2-fde-dip.c: Likewise.
This commit is contained in:
Sandra Loosemore
2024-11-23 23:59:13 +00:00
parent 7d92901c87
commit e876acab6c
157 changed files with 18 additions and 18095 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
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@@ -102,8 +102,6 @@ moxie port Anthony Green <green@moxielogic.com>
msp430 port Nick Clifton <nickc@redhat.com>
nds32 port Chung-Ju Wu <jasonwucj@gmail.com>
nds32 port Shiva Chen <shiva0217@gmail.com>
nios2 port Chung-Lin Tang <cltang@baylibre.com>
nios2 port Sandra Loosemore <sloosemore@baylibre.com>
nvptx port Tom de Vries <tdevries@suse.de>
nvptx port Thomas Schwinge <tschwinge@baylibre.com>
or1k port Stafford Horne <shorne@gmail.com>

5
config/mt-nios2-elf
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@@ -1,5 +0,0 @@
# We build library code with -mno-gpopt so that it can be linked with
# larger executables with small-data sections that exceed the 16-bit
# offset range for GP-relative addressing.
CFLAGS_FOR_TARGET += -mno-gpopt
CXXFLAGS_FOR_TARGET += -mno-gpopt

3
configure vendored
View File

@@ -10742,9 +10742,6 @@ case "${target}" in
mips*-*-*linux* | mips*-*-gnu*)
target_makefile_frag="config/mt-mips-gnu"
;;
nios2-*-elf*)
target_makefile_frag="config/mt-nios2-elf"
;;
*-*-linux-android*)
target_makefile_frag="config/mt-android"
;;

3
configure.ac
View File

@@ -2978,9 +2978,6 @@ case "${target}" in
mips*-*-*linux* | mips*-*-gnu*)
target_makefile_frag="config/mt-mips-gnu"
;;
nios2-*-elf*)
target_makefile_frag="config/mt-nios2-elf"
;;
*-*-linux-android*)
target_makefile_frag="config/mt-android"
;;

2
contrib/config-list.mk
View File

@@ -78,8 +78,6 @@ LIST = \
moxie-uclinux moxie-rtems \
msp430-elf msp430-elfbare \
nds32le-elf nds32be-elf \
nios2-elfOPT-enable-obsolete nios2-linux-gnuOPT-enable-obsolete \
nios2-rtemsOPT-enable-obsolete \
nvptx-none \
or1k-elf or1k-linux-uclibc or1k-linux-musl or1k-rtems \
pdp11-aout \

43
gcc/common/config/nios2/nios2-common.cc
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@@ -1,43 +0,0 @@
/* Common hooks for Altera Nios II.
Copyright (C) 2012-2024 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "diagnostic-core.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
static const struct default_options nios2_option_optimization_table[] =
{
{ OPT_LEVELS_3_PLUS, OPT_mfast_sw_div, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE nios2_option_optimization_table
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

35
gcc/config.gcc
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@@ -273,7 +273,6 @@ esac
# Obsolete configurations.
case ${target} in
ia64*-*-hpux* | ia64*-*-*vms* | ia64*-*-elf* \
| nios2*-*-* \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
@@ -514,10 +513,6 @@ nds32*)
esac
extra_objs="nds32-cost.o nds32-intrinsic.o nds32-isr.o nds32-md-auxiliary.o nds32-pipelines-auxiliary.o nds32-predicates.o nds32-memory-manipulation.o nds32-fp-as-gp.o nds32-relax-opt.o nds32-utils.o"
;;
nios2-*-*)
cpu_type=nios2
extra_options="${extra_options} g.opt"
;;
nvptx-*-*)
cpu_type=nvptx
c_target_objs="nvptx-c.o"
@@ -2913,23 +2908,6 @@ nds32*-*-*)
tm_defines="${tm_defines} TARGET_DEFAULT_EXT_DSP=1"
fi
;;
nios2-*-*)
tm_file="elfos.h ${tm_file}"
tmake_file="${tmake_file} nios2/t-nios2"
case ${target} in
nios2-*-linux*)
tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h nios2/linux.h "
;;
nios2-*-elf*)
tm_file="${tm_file} newlib-stdint.h nios2/elf.h"
extra_options="${extra_options} nios2/elf.opt"
;;
nios2-*-rtems*)
tm_file="${tm_file} newlib-stdint.h nios2/rtems.h rtems.h"
tmake_file="${tmake_file} t-rtems nios2/t-rtems"
;;
esac
;;
nvptx-*)
tm_file="${tm_file} newlib-stdint.h"
use_gcc_stdint=wrap
@@ -5596,19 +5574,6 @@ case "${target}" in
;;
nios2*-*-*)
supported_defaults="arch"
case "$with_arch" in
"" | r1 | r2)
# OK
;;
*)
echo "Unknown arch used in --with-arch=$with_arch" 1>&2
exit 1
;;
esac
;;
nvptx-*)
supported_defaults=arch
TM_MULTILIB_CONFIG=$with_arch

6
gcc/config.in
View File

@@ -689,12 +689,6 @@
#endif
/* Define if your assembler supports %gotoff relocation syntax. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_NIOS2_GOTOFF_RELOCATION
#endif
/* Define if your assembler supports the -no-mul-bug-abort option. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_NO_MUL_BUG_ABORT_OPTION

118
gcc/config/nios2/constraints.md
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@@ -1,118 +0,0 @@
;; Constraint definitions for Altera Nios II.
;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
;; Contributed by Chung-Lin Tang <cltang@codesourcery.com>
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; We use the following constraint letters for constants
;;
;; I: -32768 to 32767
;; J: 0 to 65535
;; K: $nnnn0000 for some nnnn
;; P: Under R2, $nnnnffff or $ffffnnnn for some nnnn
;; L: 0 to 31 (for shift counts)
;; M: 0
;; N: 0 to 255 (for custom instruction numbers)
;; O: 0 to 31 (for control register numbers)
;; U: -32768 to 32767 under R1, -2048 to 2047 under R2
;;
;; We use the following constraint letters for memory constraints
;;
;; v: memory operands for R2 load/store exclusive instructions
;; w: memory operands for load/store IO and cache instructions
;;
;; We use the following built-in register classes:
;;
;; r: general purpose register (r0..r31)
;; m: memory operand
;;
;; Plus, we define the following constraint strings:
;;
;; S: symbol that is in the "small data" area
;; Register constraints
(define_register_constraint "c" "IJMP_REGS"
"A register suitable for an indirect jump.")
(define_register_constraint "j" "SIB_REGS"
"A register suitable for an indirect sibcall.")
;; Integer constraints
(define_constraint "I"
"A signed 16-bit constant (for arithmetic instructions)."
(and (match_code "const_int")
(match_test "SMALL_INT (ival)")))
(define_constraint "J"
"An unsigned 16-bit constant (for logical instructions)."
(and (match_code "const_int")
(match_test "SMALL_INT_UNSIGNED (ival)")))
(define_constraint "K"
"An unsigned 16-bit high constant (for logical instructions)."
(and (match_code "const_int")
(match_test "UPPER16_INT (ival)")))
(define_constraint "L"
"An unsigned 5-bit constant (for shift counts)."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 31")))
(define_constraint "M"
"Integer zero."
(and (match_code "const_int")
(match_test "ival == 0")))
(define_constraint "N"
"An unsigned 8-bit constant (for custom instruction codes)."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 255")))
(define_constraint "O"
"An unsigned 5-bit constant (for control register numbers)."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 31")))
(define_constraint "P"
"An immediate operand for R2 andchi/andci instructions."
(and (match_code "const_int")
(match_test "TARGET_ARCH_R2 && ANDCLEAR_INT (ival)")))
(define_constraint "S"
"An immediate stored in small data, accessible by GP, or by offset from r0."
(match_test "gprel_constant_p (op) || r0rel_constant_p (op)"))
(define_constraint "T"
"A constant unspec offset representing a relocation."
(match_test "nios2_unspec_reloc_p (op)"))
(define_constraint "U"
"A 12-bit or 16-bit constant (for RDPRS and DCACHE)."
(and (match_code "const_int")
(if_then_else (match_test "TARGET_ARCH_R2")
(match_test "SMALL_INT12 (ival)")
(match_test "SMALL_INT (ival)"))))
(define_memory_constraint "v"
"A memory operand suitable for R2 load/store exclusive instructions."
(match_operand 0 "ldstex_memory_operand"))
(define_memory_constraint "w"
"A memory operand suitable for load/store IO and cache instructions."
(match_operand 0 "ldstio_memory_operand"))

61
gcc/config/nios2/elf.h
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@@ -1,61 +0,0 @@
/* Definitions of ELF target support for Altera Nios II.
Copyright (C) 2012-2024 Free Software Foundation, Inc.
Contributed by Jonah Graham (jgraham@altera.com),
Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com).
Contributed by Mentor Graphics, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Specs to support the additional command-line options for Nios II ELF
toolchains. */
/* -msmallc chooses an alternate C library.
-msys-lib= specifies an additional low-level system/hosting library and
is typically used to suck in a library provided by a HAL BSP. */
#undef LIB_SPEC
#define LIB_SPEC \
"--start-group %{msmallc: -lsmallc} %{!msmallc: -lc} -lgcc \
%{msys-lib=*: -l%*} \
--end-group \
"
/* Linking with -mhal suppresses inclusion of the GCC-provided crt* begin/end
code. Normally in this case you also link with -msys-crt0= to specify
the startup code provided by the HAL BSP instead. */
#undef STARTFILE_SPEC
#define STARTFILE_SPEC \
"%{mhal:" \
"%{msys-crt0=*:%*} %{!msys-crt0=*:crt0%O%s} " \
"%{msys-crt0=:%eYou need a C startup file for -msys-crt0=};" \
":crti%O%s crtbegin%O%s}"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "%{!mhal:crtend%O%s crtn%O%s}"
/* The ELF target doesn't support the Nios II Linux ABI. */
#define TARGET_LINUX_ABI 0
/* Default -fdelete-null-pointer-checks to off, to prevent the compiler
from treating accesses to address zero as traps. On bare-metal Nios II
targets address zero may legitimately be mapped to memory (e.g., the
hardware description may specify this as the address of the interrupt
vector). Users can override this on the command line to get the
additional optimizations it enables. */
#define SUBTARGET_OVERRIDE_OPTIONS \
if (flag_delete_null_pointer_checks < 0) \
flag_delete_null_pointer_checks = 0

38
gcc/config/nios2/elf.opt
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@@ -1,38 +0,0 @@
; Options for the Altera Nios II port of the compiler.
; Copyright (C) 2012-2024 Free Software Foundation, Inc.
; Contributed by Altera and Mentor Graphics, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3, or (at your option)
; any later version.
;
; GCC is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
; These additional options are supported for ELF (bare-metal) Nios II
; toolchains.
msmallc
Target RejectNegative
Link with a limited version of the C library.
msys-lib=
Target RejectNegative Joined Var(nios2_sys_lib_string)
Name of system library to link against.
msys-crt0=
Target RejectNegative Joined Var(nios2_sys_crt0_string)
Name of the startfile.
mhal
Target RejectNegative
Link with HAL BSP.

14
gcc/config/nios2/elf.opt.urls
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@@ -1,14 +0,0 @@
; Autogenerated by regenerate-opt-urls.py from gcc/config/nios2/elf.opt and generated HTML
msmallc
UrlSuffix(gcc/Nios-II-Options.html#index-msmallc)
msys-lib=
UrlSuffix(gcc/Nios-II-Options.html#index-msys-lib)
msys-crt0=
UrlSuffix(gcc/Nios-II-Options.html#index-msys-crt0)
mhal
UrlSuffix(gcc/Nios-II-Options.html#index-mhal)

4190
gcc/config/nios2/ldstwm.md
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File diff suppressed because it is too large Load Diff

53
gcc/config/nios2/linux.h
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@@ -1,53 +0,0 @@
/* Definitions of target support for Altera Nios II systems
running GNU/Linux with ELF format.
Copyright (C) 2012-2024 Free Software Foundation, Inc.
Contributed by Mentor Graphics, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
GNU_USER_TARGET_OS_CPP_BUILTINS(); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-nios2.so.1"
#undef MUSL_DYNAMIC_LINKER
#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-nios2.so.1"
#undef LINK_SPEC
#define LINK_SPEC LINK_SPEC_ENDIAN \
"%{shared:-shared} \
%{!shared: \
%{!static: \
%{rdynamic:-export-dynamic} \
-dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \
%{static:-static}}"
/* This toolchain implements the ABI for Linux Systems documented in the
Nios II Processor Reference Handbook. */
#define TARGET_LINUX_ABI 1
/* For Linux, we have access to kernel support for atomic operations,
add initialization for __sync_* builtins. */
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS nios2_init_libfuncs

277
gcc/config/nios2/nios2-ldstwm.sml
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@@ -1,277 +0,0 @@
(* Auto-generate Nios II R2 CDX ldwm/stwm/push.n/pop.n patterns
Copyright (C) 2014-2024 Free Software Foundation, Inc.
Contributed by Mentor Graphics.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>.
This is a Standard ML program. There are multiple Standard ML
implementations widely available. We recommend the MLton optimizing
SML compiler, due to its ease of creating a standalone executable.
http://www.mlton.org/
Or from your favourite OS's friendly packaging system. Tested with
MLton Release 20130715, though other versions will probably work too.
Run with:
mlton -output a.out /path/to/gcc/config/nios2/nios2-ldstwm.sml
./a.out >/path/to/gcc/config/nios2/ldstwm.md
*)
datatype ld_st = ld | st;
datatype push_pop = push | pop;
datatype inc_dec = inc | dec;
fun for ls f = map f ls;
fun conds cond str = if cond then str else "";
fun ints n = if n>=0 then (Int.toString n) else ("-" ^ (Int.toString (~n)));
fun pushpop_pattern pptype n fp =
let
val sp_reg = "(reg:SI SP_REGNO)";
val ra_reg = "(reg:SI RA_REGNO)";
val fp_reg = "(reg:SI FP_REGNO)";
fun sets lhs rhs = "(set " ^ lhs ^
(if pptype=push then " "
else " ") ^ rhs ^ ")";
val sp_adj =
"(set " ^ sp_reg ^ "\n " ^
"(plus:SI " ^ sp_reg ^
" (match_operand 1 \"const_int_operand\" \"\")))";
fun reg i regi = "(reg:SI " ^ (ints regi) ^ ")";
fun mem i opndi =
if pptype=push then
"(mem:SI (plus:SI (reg:SI SP_REGNO) (const_int " ^ (ints (~4*i)) ^ ")))"
else
"(match_operand:SI " ^
(ints opndi) ^ " \"stack_memory_operand\" \"\")";
val start = 1 + (if fp then 2 else 1);
val lim = n + (if fp then 2 else 1);
fun set_elt i regi opndi =
if pptype=push then (sets (mem i opndi) (reg i regi))
else (sets (reg i regi) (mem i opndi));
fun get_elt_list (i, regi, opndi) =
if i > lim then []
else (set_elt i regi opndi) :: get_elt_list (i+1, regi-1, opndi+1);
val set_elements = get_elt_list (start, 16+n-1, start+1);
val ra_set = if pptype=push then sets (mem 1 2) ra_reg
else sets ra_reg (mem 1 2);
val fp_set = (conds fp (if pptype=push then sets (mem 2 3) fp_reg
else sets fp_reg (mem 2 3)));
val ret = (conds (pptype=pop) "(return)");
val element_list =
List.filter (fn x => x<>"")
([ret, sp_adj, ra_set, fp_set] @ set_elements);
fun reg_index i = 16 + n - i;
fun pop_opnds 0 spl = (conds fp ("fp" ^ spl)) ^ "ra"
| pop_opnds n spl = "r" ^ (ints (reg_index n)) ^ spl ^ (pop_opnds (n-1) spl);
fun push_opnds 0 spl = "ra" ^ (conds fp (spl ^ "fp"))
| push_opnds n spl = (push_opnds (n-1) spl) ^ spl ^ "r" ^ (ints (reg_index n));
val spadj_opnd = if pptype=push then 2 else (start+n);
val spadj = ints spadj_opnd;
val regsave_num = n + (if fp then 2 else 1);
val ppname = if pptype=push then "push" else "pop";
val name = if pptype=push then "push" ^ "_" ^ (push_opnds n "_")
else "pop" ^ "_" ^ (pop_opnds n "_");
in
"(define_insn \"*cdx_" ^ name ^ "\"\n" ^
" [(match_parallel 0 \"" ^
(conds (pptype=pop) "pop_operation") ^ "\"\n" ^
" [" ^ (String.concatWith ("\n ") element_list) ^ "])]\n" ^
" \"TARGET_HAS_CDX && XVECLEN (operands[0], 0) == " ^
(ints (length element_list)) ^
(conds (pptype=push)
("\n && (-INTVAL (operands[1]) & 3) == 0\n" ^
" && (-INTVAL (operands[1]) - " ^
(ints (4*regsave_num)) ^ ") <= 60")) ^
"\"\n" ^
(if pptype=pop then
"{\n" ^
" rtx x = XEXP (operands[" ^ spadj ^ "], 0);\n" ^
" operands[" ^ spadj ^ "] = REG_P (x) ? const0_rtx : XEXP (x, 1);\n" ^
" return \"pop.n\\\\t{" ^ (pop_opnds n ", ") ^ "}, %" ^ spadj ^ "\";\n" ^
"}\n"
else
"{\n" ^
" operands[" ^ spadj ^ "] = " ^
"GEN_INT (-INTVAL (operands[1]) - " ^ (ints (4*regsave_num)) ^ ");\n" ^
" return \"push.n\\\\t{" ^ (push_opnds n ", ") ^ "}, %" ^ spadj ^ "\";\n" ^
"}\n") ^
" [(set_attr \"type\" \"" ^ ppname ^ "\")])\n\n"
end;
fun ldstwm_pattern ldst n id wb pc =
let
val ldstwm = (if ldst=ld then "ldwm" else "stwm");
val name = "*cdx_" ^ ldstwm ^ (Int.toString n) ^
(if id=inc then "_inc" else "_dec") ^
(conds wb "_wb") ^ (conds pc "_ret");
val base_reg_referenced_p = ref false;
val base_regno = ints (n+1);
fun plus_addr base offset =
"(plus:SI " ^ base ^ " (const_int " ^ (ints offset) ^ "))";
fun base_reg () =
if !base_reg_referenced_p then
"(match_dup " ^ base_regno ^ ")"
else (base_reg_referenced_p := true;
"(match_operand:SI " ^ base_regno ^
" \"register_operand\" \"" ^ (conds wb "+&") ^ "r\")");
fun reg i = "(match_operand:SI " ^ (ints i) ^
" \"nios2_hard_register_operand\" \"" ^
(conds (ldst=ld) "") ^ "\")";
fun addr 1 = if id=inc then base_reg ()
else plus_addr (base_reg ()) (~4)
| addr i = let val offset = if id=inc then (i-1)*4 else (~i*4)
in plus_addr (base_reg ()) offset end;
fun mem i = "(mem:SI " ^ (addr i) ^ ")";
fun lhs i = if ldst=ld then reg i else mem i;
fun rhs i = if ldst=st then reg i else mem i;
fun sets lhs rhs = "(set " ^ lhs ^ "\n " ^ rhs ^ ")";
fun set_elements i =
if i > n then []
else (sets (lhs i) (rhs i)) :: (set_elements (i+1));
fun opnds 1 = "%1"
| opnds n = opnds(n-1) ^ ", %" ^ (Int.toString n);
val asm_template = ldstwm ^ "\\\\t{" ^ (opnds n) ^ "}" ^
(if id=inc
then ", (%" ^ base_regno ^ ")++"
else ", --(%" ^ base_regno ^ ")") ^
(conds wb ", writeback") ^
(conds pc ", ret");
val wbtmp =
if wb then
(sets (base_reg ())
(plus_addr (base_reg ())
((if id=inc then n else ~n)*4)))
else "";
val pctmp = conds pc "(return)";
val set_list = List.filter (fn x => x<>"")
([pctmp, wbtmp] @ (set_elements 1));
in
if ldst=st andalso pc then ""
else
"(define_insn \"" ^ name ^ "\"\n" ^
" [(match_parallel 0 \"" ^ ldstwm ^ "_operation\"\n" ^
" [" ^ (String.concatWith ("\n ") set_list) ^ "])]\n" ^
" \"TARGET_HAS_CDX && XVECLEN (operands[0], 0) == " ^
(ints (length set_list)) ^ "\"\n" ^
" \"" ^ asm_template ^ "\"\n" ^
" [(set_attr \"type\" \"" ^ ldstwm ^ "\")])\n\n"
end;
fun peephole_pattern ldst n scratch_p =
let
fun sets lhs rhs = "(set " ^ lhs ^ "\n " ^ rhs ^ ")";
fun single_set i indent =
let val reg = "(match_operand:SI " ^ (ints i) ^
" \"register_operand\" \"\")";
val mem = "(match_operand:SI " ^ (ints (i+n)) ^
" \"memory_operand\" \"\")";
in
if ldst=ld then sets reg mem
else sets mem reg
end;
fun single_sets i =
if i=n then []
else (single_set i " ") :: (single_sets (i+1));
val scratch = ints (2*n);
val peephole_elements =
let val tmp = single_sets 0 in
if scratch_p
then (["(match_scratch:SI " ^ scratch ^ " \"r\")"] @
tmp @
["(match_dup " ^ scratch ^ ")"])
else tmp
end;
in
"(define_peephole2\n" ^
" [" ^ (String.concatWith ("\n ") peephole_elements) ^ "]\n" ^
" \"TARGET_HAS_CDX\"\n" ^
" [(const_int 0)]\n" ^
"{\n" ^
" if (gen_ldstwm_peep (" ^
(if ldst=st then "false" else "true") ^ ", " ^ (ints n) ^ ", " ^
(if scratch_p then ("operands[" ^ scratch ^ "]") else "NULL_RTX") ^
", operands))\n" ^
" DONE;\n" ^
" else\n" ^
" FAIL;\n" ^
"})\n\n"
end;
print
("/* Nios II R2 CDX ldwm/stwm/push.h/pop.n instruction patterns.\n" ^
" This file was automatically generated using nios2-ldstwm.sml.\n" ^
" Please do not edit manually.\n" ^
"\n" ^
" Copyright (C) 2014-2024 Free Software Foundation, Inc.\n" ^
" Contributed by Mentor Graphics.\n" ^
"\n" ^
" This file is part of GCC.\n" ^
"\n" ^
" GCC is free software; you can redistribute it and/or modify it\n" ^
" under the terms of the GNU General Public License as published\n" ^
" by the Free Software Foundation; either version 3, or (at your\n" ^
" option) any later version.\n" ^
"\n" ^
" GCC is distributed in the hope that it will be useful, but WITHOUT\n" ^
" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n" ^
" or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n" ^
" License for more details.\n" ^
"\n" ^
" You should have received a copy of the GNU General Public License and\n" ^
" a copy of the GCC Runtime Library Exception along with this program;\n" ^
" see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n" ^
" <http://www.gnu.org/licenses/>. */\n\n");
fun seq a b = if a=b then [b]
else a :: (seq (if a<b then a+1 else a-1) b);
(* push/pop patterns *)
for (seq 0 8) (fn n =>
for [push, pop] (fn p =>
for [true, false] (fn fp =>
print (pushpop_pattern p n fp))));
(* ldwm/stwm patterns *)
for [ld, st] (fn l =>
for (seq 1 12) (fn n =>
for [inc, dec] (fn id =>
for [true, false] (fn wb =>
for [true, false] (fn pc =>
print (ldstwm_pattern l n id wb pc))))));
(* peephole patterns *)
for [ld, st] (fn l =>
for (seq 12 2) (fn n =>
print (peephole_pattern l n true)));

88
gcc/config/nios2/nios2-opts.h
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@@ -1,88 +0,0 @@
/* Definitions for option handling for Nios II.
Copyright (C) 2013-2024 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef NIOS2_OPTS_H
#define NIOS2_OPTS_H
/* Enumerate the possible -mgpopt choices. */
enum nios2_gpopt_type
{
gpopt_unspecified = -1,
gpopt_none,
gpopt_local,
gpopt_global,
gpopt_data,
gpopt_all
};
/* Enumeration of all FPU insn codes. */
#define N2FPU_ALL_CODES \
N2FPU_CODE(fadds) N2FPU_CODE(fsubs) N2FPU_CODE(fmuls) N2FPU_CODE(fdivs) \
N2FPU_CODE(fmins) N2FPU_CODE(fmaxs) \
N2FPU_CODE(fnegs) N2FPU_CODE(fabss) N2FPU_CODE(fsqrts) \
N2FPU_CODE(fsins) N2FPU_CODE(fcoss) N2FPU_CODE(ftans) N2FPU_CODE(fatans) \
N2FPU_CODE(fexps) N2FPU_CODE(flogs) \
N2FPU_CODE(fcmpeqs) N2FPU_CODE(fcmpnes) \
N2FPU_CODE(fcmplts) N2FPU_CODE(fcmples) \
N2FPU_CODE(fcmpgts) N2FPU_CODE(fcmpges) \
\
N2FPU_CODE(faddd) N2FPU_CODE(fsubd) N2FPU_CODE(fmuld) N2FPU_CODE(fdivd) \
N2FPU_CODE(fmind) N2FPU_CODE(fmaxd) \
N2FPU_CODE(fnegd) N2FPU_CODE(fabsd) N2FPU_CODE(fsqrtd) \
N2FPU_CODE(fsind) N2FPU_CODE(fcosd) N2FPU_CODE(ftand) N2FPU_CODE(fatand) \
N2FPU_CODE(fexpd) N2FPU_CODE(flogd) \
N2FPU_CODE(fcmpeqd) N2FPU_CODE(fcmpned) \
N2FPU_CODE(fcmpltd) N2FPU_CODE(fcmpled) \
N2FPU_CODE(fcmpgtd) N2FPU_CODE(fcmpged) \
\
N2FPU_CODE(floatis) N2FPU_CODE(floatus) \
N2FPU_CODE(floatid) N2FPU_CODE(floatud) \
N2FPU_CODE(round) N2FPU_CODE(fixsi) N2FPU_CODE(fixsu) \
N2FPU_CODE(fixdi) N2FPU_CODE(fixdu) \
N2FPU_CODE(fextsd) N2FPU_CODE(ftruncds) \
\
N2FPU_CODE(fwrx) N2FPU_CODE(fwry) \
N2FPU_CODE(frdxlo) N2FPU_CODE(frdxhi) N2FPU_CODE(frdy)
enum n2fpu_code {
#define N2FPU_CODE(name) n2fpu_ ## name,
N2FPU_ALL_CODES
#undef N2FPU_CODE
n2fpu_code_num
};
/* An enumeration to indicate the custom code status; if values within 0--255
are registered to an FPU insn, or custom insn. */
enum nios2_ccs_code
{
CCS_UNUSED,
CCS_FPU,
CCS_BUILTIN_CALL
};
/* Supported Nios II Architectures. */
enum nios2_arch_type
{
ARCH_R1=1,
ARCH_R2
};
#endif

72
gcc/config/nios2/nios2-protos.h
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@@ -1,72 +0,0 @@
/* Subroutine declarations for Altera Nios II target support.
Copyright (C) 2012-2024 Free Software Foundation, Inc.
Contributed by Jonah Graham (jgraham@altera.com).
Contributed by Mentor Graphics, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_NIOS2_PROTOS_H
#define GCC_NIOS2_PROTOS_H
extern int nios2_initial_elimination_offset (int, int);
extern int nios2_can_use_return_insn (void);
extern void nios2_expand_prologue (void);
extern void nios2_expand_epilogue (bool);
extern bool nios2_expand_return (void);
extern void nios2_function_profiler (FILE *, int);
extern bool nios2_fpu_insn_enabled (enum n2fpu_code);
#ifdef RTX_CODE
extern bool nios2_large_constant_p (rtx);
extern bool nios2_large_constant_memory_operand_p (rtx);
extern rtx nios2_split_large_constant (rtx, rtx);
extern rtx nios2_split_large_constant_memory_operand (rtx);
extern bool nios2_emit_move_sequence (rtx *, machine_mode);
extern void nios2_emit_expensive_div (rtx *, machine_mode);
extern void nios2_adjust_call_address (rtx *, rtx);
extern rtx nios2_get_return_address (int);
extern void nios2_set_return_address (rtx, rtx);
extern bool nios2_validate_compare (machine_mode, rtx *, rtx *, rtx *);
extern bool nios2_validate_fpu_compare (machine_mode, rtx *, rtx *, rtx *,
bool);
extern const char * nios2_fpu_insn_asm (enum n2fpu_code);
extern const char * nios2_add_insn_asm (rtx_insn *, rtx *);
extern bool nios2_legitimate_pic_operand_p (rtx);
extern bool gprel_constant_p (rtx);
extern bool r0rel_constant_p (rtx);
extern bool nios2_regno_ok_for_base_p (int, bool);
extern bool nios2_unspec_reloc_p (rtx);
extern int nios2_label_align (rtx);
extern bool nios2_cdx_narrow_form_p (rtx_insn *);
extern bool pop_operation_p (rtx);
extern bool ldstwm_operation_p (rtx, bool);
extern bool gen_ldstwm_peep (bool, int, rtx, rtx *);
extern void nios2_adjust_reg_alloc_order (void);
extern pad_direction nios2_block_reg_padding (machine_mode, tree, int);
#endif /* RTX_CODE */
#endif /* GCC_NIOS2_PROTOS_H */

5630
gcc/config/nios2/nios2.cc
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File diff suppressed because it is too large Load Diff

540
gcc/config/nios2/nios2.h
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@@ -1,540 +0,0 @@
/* Definitions of target machine for Altera Nios II.
Copyright (C) 2012-2024 Free Software Foundation, Inc.
Contributed by Jonah Graham (jgraham@altera.com),
Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com).
Contributed by Mentor Graphics, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_NIOS2_H
#define GCC_NIOS2_H
/* Indicate R2 ISA level support. */
#define TARGET_ARCH_R2 (nios2_arch_option == ARCH_R2)
/* FPU insn codes declared here. */
#include "config/nios2/nios2-opts.h"
/* Define built-in preprocessor macros. */
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("NIOS2"); \
builtin_define_std ("nios2"); \
if (TARGET_BIG_ENDIAN) \
builtin_define_std ("nios2_big_endian"); \
else \
builtin_define_std ("nios2_little_endian"); \
builtin_define_with_int_value ( \
"__nios2_arch__", (int) nios2_arch_option); \
} \
while (0)
/* We're little endian, unless otherwise specified by defining
BIG_ENDIAN_FLAG. */
#ifndef TARGET_ENDIAN_DEFAULT
# define TARGET_ENDIAN_DEFAULT 0
#endif
/* Default target_flags if no switches specified. */
#ifndef TARGET_DEFAULT
# define TARGET_DEFAULT (MASK_HAS_MUL | TARGET_ENDIAN_DEFAULT)
#endif
#define OPTION_DEFAULT_SPECS \
{"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }
#define CC1_SPEC "%{G*}"
#if TARGET_ENDIAN_DEFAULT == 0
# define ASM_SPEC "%{!meb:-EL} %{meb:-EB} %{march=*:-march=%*}"
# define LINK_SPEC_ENDIAN "%{!meb:-EL} %{meb:-EB}"
# define MULTILIB_DEFAULTS { "EL" }
#else
# define ASM_SPEC "%{!mel:-EB} %{mel:-EL} %{march=*:-march=%*}"
# define LINK_SPEC_ENDIAN "%{!mel:-EB} %{mel:-EL}"
# define MULTILIB_DEFAULTS { "EB" }
#endif
#define LINK_SPEC LINK_SPEC_ENDIAN \
" %{shared:-shared} \
%{static:-Bstatic}"
/* Storage layout. */
#define DEFAULT_SIGNED_CHAR 1
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#define BITS_PER_WORD 32
#define UNITS_PER_WORD 4
#define POINTER_SIZE 32
#define BIGGEST_ALIGNMENT 32
#define STRICT_ALIGNMENT 1
#define FUNCTION_BOUNDARY 32
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define PREFERRED_STACK_BOUNDARY 32
#define MAX_FIXED_MODE_SIZE 64
#define LABEL_ALIGN(LABEL) nios2_label_align (LABEL)
/* Layout of source language data types. */
#define INT_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "int"
/* Basic characteristics of Nios II registers:
Regno Name
0 r0 zero always zero
1 r1 at Assembler Temporary
2-3 r2-r3 Return Location
4-7 r4-r7 Register Arguments
8-15 r8-r15 Caller Saved Registers
16-22 r16-r22 Callee Saved Registers
22 r22 Global Offset Table pointer (Linux ABI only)
23 r23 Thread pointer (Linux ABI only)
24 r24 et Exception Temporary
25 r25 bt Breakpoint Temporary
26 r26 gp Global Pointer
27 r27 sp Stack Pointer
28 r28 fp Frame Pointer
29 r29 ea Exception Return Address
30 r30 ba Breakpoint Return Address
31 r31 ra Return Address
32 ctl0 status
33 ctl1 estatus STATUS saved by exception
34 ctl2 bstatus STATUS saved by break
35 ctl3 ipri Interrupt Priority Mask
36 ctl4 ecause Exception Cause
37 pc Not an actual register
38 fake_fp Fake Frame Pointer (always eliminated)
39 fake_ap Fake Argument Pointer (always eliminated)
40 First Pseudo Register
In addition, r12 is used as the static chain register and r13, r14, and r15
are clobbered by PLT code sequences.
The definitions for all the hard register numbers are located in nios2.md.
*/
#define FIXED_REGISTERS \
{ \
/* +0 1 2 3 4 5 6 7 8 9 */ \
/* 0 */ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
/* 10 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* 20 */ 0, 0, TARGET_LINUX_ABI, TARGET_LINUX_ABI, 1, 1, 1, 1, 0, 1, \
/* 30 */ 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
}
/* Call used == caller saved + fixed regs + args + ret vals. */
#define CALL_USED_REGISTERS \
{ \
/* +0 1 2 3 4 5 6 7 8 9 */ \
/* 0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* 10 */ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
/* 20 */ 0, 0, TARGET_LINUX_ABI, TARGET_LINUX_ABI, 1, 1, 1, 1, 0, 1, \
/* 30 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
}
/* Order in which to allocate registers. Each register must be
listed once. This is the default ordering for R1 and non-CDX R2
code. For CDX, we overwrite this in ADJUST_REG_ALLOC_ORDER. */
#define REG_ALLOC_ORDER \
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, \
37, 38, 39 }
#define ADJUST_REG_ALLOC_ORDER nios2_adjust_reg_alloc_order ()
/* Caller-save costs can be less emphasized under R2 CDX, where we can
use push.n/pop.n. */
#define HONOR_REG_ALLOC_ORDER (TARGET_HAS_CDX)
/* Register Classes. */
enum reg_class
{
NO_REGS,
SIB_REGS,
IJMP_REGS,
GP_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ "NO_REGS", \
"SIB_REGS", \
"IJMP_REGS", \
"GP_REGS", \
"ALL_REGS" }
#define GENERAL_REGS ALL_REGS
#define REG_CLASS_CONTENTS \
{ \
/* NO_REGS */ { 0, 0}, \
/* SIB_REGS */ { 0xfe0c, 0}, \
/* IJMP_REGS */ { 0x7fffffff, 0}, \
/* GP_REGS */ {~0, 0}, \
/* ALL_REGS */ {~0,~0} \
}
#define GP_REG_P(REGNO) ((unsigned)(REGNO) <= LAST_GP_REG)
#define REGNO_REG_CLASS(REGNO) (GP_REG_P (REGNO) ? GP_REGS : ALL_REGS)
#define CLASS_MAX_NREGS(CLASS, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define CDX_REG_P(REGNO) \
((REGNO) == 16 || (REGNO) == 17 || ((REGNO) >= 2 && (REGNO) <= 7))
/* Tests for various kinds of constants used in the Nios II port. */
#define SMALL_INT(X) ((unsigned HOST_WIDE_INT)(X) + 0x8000 < 0x10000)
#define SMALL_INT12(X) ((unsigned HOST_WIDE_INT)(X) + 0x800 < 0x1000)
#define SMALL_INT_UNSIGNED(X) ((X) >= 0 && (X) < 0x10000)
#define UPPER16_INT(X) (((X) & 0xffff) == 0)
#define SHIFT_INT(X) ((X) >= 0 && (X) <= 31)
#define RDWRCTL_INT(X) ((X) >= 0 && (X) <= 31)
#define CUSTOM_INSN_OPCODE(X) ((X) >= 0 && (X) <= 255)
#define ANDCLEAR_INT(X) \
(((X) & 0xffff) == 0xffff || (((X) >> 16) & 0xffff) == 0xffff)
/* Say that the epilogue uses the return address register. Note that
in the case of sibcalls, the values "used by the epilogue" are
considered live at the start of the called function. */
#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == RA_REGNO)
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
functions that have frame pointers.
No definition is equivalent to always zero. */
#define EXIT_IGNORE_STACK 1
/* Trampolines use a 5-instruction sequence. */
#define TRAMPOLINE_SIZE 20
/* Stack layout. */
#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
#define FIRST_PARM_OFFSET(FUNDECL) 0
/* Before the prologue, RA lives in r31. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RA_REGNO)
#define RETURN_ADDR_RTX(C,F) nios2_get_return_address (C)
#define DWARF_FRAME_RETURN_COLUMN RA_REGNO
/* The CFA includes the pretend args. */
#define ARG_POINTER_CFA_OFFSET(FNDECL) \
(gcc_assert ((FNDECL) == current_function_decl), \
FIRST_PARM_OFFSET (FNDECL) + crtl->args.pretend_args_size)
/* Frame/arg pointer elimination settings. */
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = nios2_initial_elimination_offset ((FROM), (TO))
/* Calling convention definitions. */
typedef struct nios2_args
{
int regs_used;
} CUMULATIVE_ARGS;
#define NUM_ARG_REGS (LAST_ARG_REGNO - FIRST_ARG_REGNO + 1)
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
do { (CUM).regs_used = 0; } while (0)
#define PAD_VARARGS_DOWN \
(targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(nios2_block_reg_padding ((MODE), (TYPE), (FIRST)))
#define FUNCTION_ARG_REGNO_P(REGNO) \
((REGNO) >= FIRST_ARG_REGNO && (REGNO) <= LAST_ARG_REGNO)
/* Passing function arguments on stack. */
#define ACCUMULATE_OUTGOING_ARGS 1
/* We define TARGET_RETURN_IN_MEMORY, so set to zero. */
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Profiling. */
#define PROFILE_BEFORE_PROLOGUE
#define NO_PROFILE_COUNTERS 1
#define FUNCTION_PROFILER(FILE, LABELNO) \
nios2_function_profiler ((FILE), (LABELNO))
/* Addressing modes. */
#define CONSTANT_ADDRESS_P(X) \
(CONSTANT_P (X) && memory_address_p (SImode, X))
#define MAX_REGS_PER_ADDRESS 1
#define BASE_REG_CLASS ALL_REGS
#define INDEX_REG_CLASS NO_REGS
#define REGNO_OK_FOR_BASE_P(REGNO) nios2_regno_ok_for_base_p ((REGNO), true)
#define REGNO_OK_FOR_INDEX_P(REGNO) 0
/* Describing Relative Costs of Operations. */
#define MOVE_MAX 4
#define SLOW_BYTE_ACCESS 1
/* It is as good to call a constant function address as to call an address
kept in a register. */
#define NO_FUNCTION_CSE 1
/* Position independent code. */
#define PIC_OFFSET_TABLE_REGNUM 22
#define LEGITIMATE_PIC_OPERAND_P(X) nios2_legitimate_pic_operand_p (X)
/* Define output assembler language. */
#define ASM_APP_ON "#APP\n"
#define ASM_APP_OFF "#NO_APP\n"
#define ASM_COMMENT_START "# "
#define GLOBAL_ASM_OP "\t.global\t"
#define REGISTER_NAMES \
{ \
"zero", \
"at", \
"r2", \
"r3", \
"r4", \
"r5", \
"r6", \
"r7", \
"r8", \
"r9", \
"r10", \
"r11", \
"r12", \
"r13", \
"r14", \
"r15", \
"r16", \
"r17", \
"r18", \
"r19", \
"r20", \
"r21", \
"r22", \
"r23", \
"et", \
"bt", \
"gp", \
"sp", \
"fp", \
"ta", \
"ba", \
"ra", \
"status", \
"estatus", \
"bstatus", \
"ipri", \
"ecause", \
"pc", \
"fake_fp", \
"fake_ap", \
}
#define ADDITIONAL_REGISTER_NAMES \
{ \
{"r0", 0}, \
{"r1", 1}, \
{"r24", 24}, \
{"r25", 25}, \
{"r26", 26}, \
{"r27", 27}, \
{"r28", 28}, \
{"r29", 29}, \
{"r30", 30}, \
{"r31", 31} \
}
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
do \
{ \
fputs (integer_asm_op (POINTER_SIZE / BITS_PER_UNIT, TRUE), FILE); \
fprintf (FILE, ".L%u\n", (unsigned) (VALUE)); \
} \
while (0)
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)\
do \
{ \
fputs (integer_asm_op (POINTER_SIZE / BITS_PER_UNIT, TRUE), STREAM); \
fprintf (STREAM, ".L%u-.L%u\n", (unsigned) (VALUE), (unsigned) (REL)); \
} \
while (0)
/* Section directives. */
/* Output before read-only data. */
#define TEXT_SECTION_ASM_OP "\t.section\t.text"
/* Output before writable data. */
#define DATA_SECTION_ASM_OP "\t.section\t.data"
/* Output before uninitialized data. */
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
/* Output before 'small' uninitialized data. */
#define SBSS_SECTION_ASM_OP "\t.section\t.sbss"
#ifndef USED_FOR_TARGET
/* Default the definition of "small data" to 8 bytes. */
extern unsigned HOST_WIDE_INT nios2_section_threshold;
#endif
#define NIOS2_DEFAULT_GVALUE 8
/* This says how to output assembler code to declare an
uninitialized external linkage data object. Under SVR4,
the linker seems to want the alignment of data objects
to depend on their types. We do exactly that here. */
#undef COMMON_ASM_OP
#define COMMON_ASM_OP "\t.comm\t"
#define ASM_OUTPUT_ALIGN(FILE, LOG) \
do { \
fprintf ((FILE), "%s%d\n", ALIGN_ASM_OP, (LOG)); \
} while (0)
#undef ASM_OUTPUT_ALIGNED_COMMON
#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
do \
{ \
fprintf ((FILE), "%s", COMMON_ASM_OP); \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", (SIZE), \
(ALIGN) / BITS_PER_UNIT); \
} \
while (0)
/* This says how to output assembler code to declare an
uninitialized internal linkage data object. Under SVR4,
the linker seems to want the alignment of data objects
to depend on their types. We do exactly that here. */
#undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
do { \
if (targetm.in_small_data_p (DECL)) \
switch_to_section (sbss_section); \
else \
switch_to_section (bss_section); \
ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
if (!flag_inhibit_size_directive) \
ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \
ASM_OUTPUT_LABEL(FILE, NAME); \
ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \
} while (0)
/* Put the jump tables in .text because when using position-independent code,
Nios II elf has no relocation that can represent arbitrary differences
between symbols in different sections. */
#define JUMP_TABLES_IN_TEXT_SECTION 1
/* Exception handling. */
/* Describe __builtin_eh_return. */
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, LAST_RETVAL_REGNO)
#define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_ARG_REGNO - FIRST_ARG_REGNO) \
? (N) + FIRST_ARG_REGNO : INVALID_REGNUM)
/* For PIC, use indirect for global references; it'll end up using a dynamic
relocation, which we want to keep out of read-only EH sections.
For local references, we want to use GOT-relative offsets provided
the assembler supports them. For non-PIC, use an absolute encoding. */
#ifdef HAVE_AS_NIOS2_GOTOFF_RELOCATION
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
(flag_pic \
? ((GLOBAL) \
? DW_EH_PE_indirect | DW_EH_PE_absptr \
: DW_EH_PE_datarel | DW_EH_PE_sdata4) \
: DW_EH_PE_absptr)
#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
do { \
if (((ENCODING) & 0xf0) == DW_EH_PE_datarel) \
{ \
fputs ("\t.4byte %gotoff(", FILE); \
output_addr_const (FILE, ADDR); \
fputs (")", FILE); \
goto DONE; \
} \
} while (0)
#else
/* We don't have %gotoff support in the assembler. Fall back to the encoding
it used to use instead before the assembler was fixed. This has known
bugs but mostly works. */
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
(flag_pic \
? ((GLOBAL) \
? DW_EH_PE_indirect | DW_EH_PE_absptr \
: DW_EH_PE_aligned) \
: DW_EH_PE_absptr)
#endif
/* Misc. parameters. */
#define STORE_FLAG_VALUE 1
#define Pmode SImode
#define FUNCTION_MODE QImode
#define CASE_VECTOR_MODE Pmode
#define LOAD_EXTEND_OP(MODE) (ZERO_EXTEND)
#define WORD_REGISTER_OPERATIONS 1
#endif /* GCC_NIOS2_H */

1311
gcc/config/nios2/nios2.md
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File diff suppressed because it is too large Load Diff

596
gcc/config/nios2/nios2.opt
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@@ -1,596 +0,0 @@
; Options for the Altera Nios II port of the compiler.
; Copyright (C) 2012-2024 Free Software Foundation, Inc.
; Contributed by Altera and Mentor Graphics, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3, or (at your option)
; any later version.
;
; GCC is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
HeaderInclude
config/nios2/nios2-opts.h
TargetSave
int saved_fpu_custom_code[n2fpu_code_num]
TargetSave
enum nios2_ccs_code saved_custom_code_status[256]
TargetSave
int saved_custom_code_index[256]
mhw-div
Target Mask(HAS_DIV)
Enable DIV, DIVU.
mhw-mul
Target Mask(HAS_MUL)
Enable MUL instructions.
mhw-mulx
Target Mask(HAS_MULX)
Enable MULX instructions, assume fast shifter.
mfast-sw-div
Target Mask(FAST_SW_DIV)
Use table based fast divide (default at -O3).
mbypass-cache
Target Mask(BYPASS_CACHE)
All memory accesses use I/O load/store instructions.
mno-cache-volatile
Target RejectNegative Mask(BYPASS_CACHE_VOLATILE)
Volatile memory accesses use I/O load/store instructions.
mcache-volatile
Target RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE)
Volatile memory accesses do not use I/O load/store instructions.
mgpopt=
Target RejectNegative Joined Enum(nios2_gpopt_type) Var(nios2_gpopt_option) Init(gpopt_unspecified)
Enable/disable GP-relative addressing.
Enum
Name(nios2_gpopt_type) Type(enum nios2_gpopt_type)
Valid options for GP-relative addressing (for -mgpopt):
EnumValue
Enum(nios2_gpopt_type) String(none) Value(gpopt_none)
EnumValue
Enum(nios2_gpopt_type) String(local) Value(gpopt_local)
EnumValue
Enum(nios2_gpopt_type) String(global) Value(gpopt_global)
EnumValue
Enum(nios2_gpopt_type) String(data) Value(gpopt_data)
EnumValue
Enum(nios2_gpopt_type) String(all) Value(gpopt_all)
mgpopt
Target RejectNegative Var(nios2_gpopt_option, gpopt_local)
Equivalent to -mgpopt=local.
mno-gpopt
Target RejectNegative Var(nios2_gpopt_option, gpopt_none)
Equivalent to -mgpopt=none.
meb
Target RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order.
mel
Target RejectNegative InverseMask(BIG_ENDIAN)
Use little-endian byte order.
mcustom-fpu-cfg=
Target RejectNegative Joined Var(nios2_custom_fpu_cfg_string)
Floating point custom instruction configuration name.
mno-custom-ftruncds
Target RejectNegative Var(nios2_custom_ftruncds, -1)
Do not use the ftruncds custom instruction.
mcustom-ftruncds=
Target RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1)
Integer id (N) of ftruncds custom instruction.
mno-custom-fextsd
Target RejectNegative Var(nios2_custom_fextsd, -1)
Do not use the fextsd custom instruction.
mcustom-fextsd=
Target RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1)
Integer id (N) of fextsd custom instruction.
mno-custom-fixdu
Target RejectNegative Var(nios2_custom_fixdu, -1)
Do not use the fixdu custom instruction.
mcustom-fixdu=
Target RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1)
Integer id (N) of fixdu custom instruction.
mno-custom-fixdi
Target RejectNegative Var(nios2_custom_fixdi, -1)
Do not use the fixdi custom instruction.
mcustom-fixdi=
Target RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1)
Integer id (N) of fixdi custom instruction.
mno-custom-fixsu
Target RejectNegative Var(nios2_custom_fixsu, -1)
Do not use the fixsu custom instruction.
mcustom-fixsu=
Target RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1)
Integer id (N) of fixsu custom instruction.
mno-custom-fixsi
Target RejectNegative Var(nios2_custom_fixsi, -1)
Do not use the fixsi custom instruction.
mcustom-fixsi=
Target RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1)
Integer id (N) of fixsi custom instruction.
mno-custom-floatud
Target RejectNegative Var(nios2_custom_floatud, -1)
Do not use the floatud custom instruction.
mcustom-floatud=
Target RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1)
Integer id (N) of floatud custom instruction.
mno-custom-floatid
Target RejectNegative Var(nios2_custom_floatid, -1)
Do not use the floatid custom instruction.
mcustom-floatid=
Target RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1)
Integer id (N) of floatid custom instruction.
mno-custom-floatus
Target RejectNegative Var(nios2_custom_floatus, -1)
Do not use the floatus custom instruction.
mcustom-floatus=
Target RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1)
Integer id (N) of floatus custom instruction.
mno-custom-floatis
Target RejectNegative Var(nios2_custom_floatis, -1)
Do not use the floatis custom instruction.
mcustom-floatis=
Target RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1)
Integer id (N) of floatis custom instruction.
mno-custom-fcmpned
Target RejectNegative Var(nios2_custom_fcmpned, -1)
Do not use the fcmpned custom instruction.
mcustom-fcmpned=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1)
Integer id (N) of fcmpned custom instruction.
mno-custom-fcmpeqd
Target RejectNegative Var(nios2_custom_fcmpeqd, -1)
Do not use the fcmpeqd custom instruction.
mcustom-fcmpeqd=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1)
Integer id (N) of fcmpeqd custom instruction.
mno-custom-fcmpged
Target RejectNegative Var(nios2_custom_fcmpged, -1)
Do not use the fcmpged custom instruction.
mcustom-fcmpged=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1)
Integer id (N) of fcmpged custom instruction.
mno-custom-fcmpgtd
Target RejectNegative Var(nios2_custom_fcmpgtd, -1)
Do not use the fcmpgtd custom instruction.
mcustom-fcmpgtd=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1)
Integer id (N) of fcmpgtd custom instruction.
mno-custom-fcmpled
Target RejectNegative Var(nios2_custom_fcmpled, -1)
Do not use the fcmpled custom instruction.
mcustom-fcmpled=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1)
Integer id (N) of fcmpled custom instruction.
mno-custom-fcmpltd
Target RejectNegative Var(nios2_custom_fcmpltd, -1)
Do not use the fcmpltd custom instruction.
mcustom-fcmpltd=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1)
Integer id (N) of fcmpltd custom instruction.
mno-custom-flogd
Target RejectNegative Var(nios2_custom_flogd, -1)
Do not use the flogd custom instruction.
mcustom-flogd=
Target RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1)
Integer id (N) of flogd custom instruction.
mno-custom-fexpd
Target RejectNegative Var(nios2_custom_fexpd, -1)
Do not use the fexpd custom instruction.
mcustom-fexpd=
Target RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1)
Integer id (N) of fexpd custom instruction.
mno-custom-fatand
Target RejectNegative Var(nios2_custom_fatand, -1)
Do not use the fatand custom instruction.
mcustom-fatand=
Target RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1)
Integer id (N) of fatand custom instruction.
mno-custom-ftand
Target RejectNegative Var(nios2_custom_ftand, -1)
Do not use the ftand custom instruction.
mcustom-ftand=
Target RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1)
Integer id (N) of ftand custom instruction.
mno-custom-fsind
Target RejectNegative Var(nios2_custom_fsind, -1)
Do not use the fsind custom instruction.
mcustom-fsind=
Target RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1)
Integer id (N) of fsind custom instruction.
mno-custom-fcosd
Target RejectNegative Var(nios2_custom_fcosd, -1)
Do not use the fcosd custom instruction.
mcustom-fcosd=
Target RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1)
Integer id (N) of fcosd custom instruction.
mno-custom-fsqrtd
Target RejectNegative Var(nios2_custom_fsqrtd, -1)
Do not use the fsqrtd custom instruction.
mcustom-fsqrtd=
Target RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1)
Integer id (N) of fsqrtd custom instruction.
mno-custom-fabsd
Target RejectNegative Var(nios2_custom_fabsd, -1)
Do not use the fabsd custom instruction.
mcustom-fabsd=
Target RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1)
Integer id (N) of fabsd custom instruction.
mno-custom-fnegd
Target RejectNegative Var(nios2_custom_fnegd, -1)
Do not use the fnegd custom instruction.
mcustom-fnegd=
Target RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1)
Integer id (N) of fnegd custom instruction.
mno-custom-fmaxd
Target RejectNegative Var(nios2_custom_fmaxd, -1)
Do not use the fmaxd custom instruction.
mcustom-fmaxd=
Target RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1)
Integer id (N) of fmaxd custom instruction.
mno-custom-fmind
Target RejectNegative Var(nios2_custom_fmind, -1)
Do not use the fmind custom instruction.
mcustom-fmind=
Target RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1)
Integer id (N) of fmind custom instruction.
mno-custom-fdivd
Target RejectNegative Var(nios2_custom_fdivd, -1)
Do not use the fdivd custom instruction.
mcustom-fdivd=
Target RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1)
Integer id (N) of fdivd custom instruction.
mno-custom-fmuld
Target RejectNegative Var(nios2_custom_fmuld, -1)
Do not use the fmuld custom instruction.
mcustom-fmuld=
Target RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1)
Integer id (N) of fmuld custom instruction.
mno-custom-fsubd
Target RejectNegative Var(nios2_custom_fsubd, -1)
Do not use the fsubd custom instruction.
mcustom-fsubd=
Target RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1)
Integer id (N) of fsubd custom instruction.
mno-custom-faddd
Target RejectNegative Var(nios2_custom_faddd, -1)
Do not use the faddd custom instruction.
mcustom-faddd=
Target RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1)
Integer id (N) of faddd custom instruction.
mno-custom-fcmpnes
Target RejectNegative Var(nios2_custom_fcmpnes, -1)
Do not use the fcmpnes custom instruction.
mcustom-fcmpnes=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1)
Integer id (N) of fcmpnes custom instruction.
mno-custom-fcmpeqs
Target RejectNegative Var(nios2_custom_fcmpeqs, -1)
Do not use the fcmpeqs custom instruction.
mcustom-fcmpeqs=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1)
Integer id (N) of fcmpeqs custom instruction.
mno-custom-fcmpges
Target RejectNegative Var(nios2_custom_fcmpges, -1)
Do not use the fcmpges custom instruction.
mcustom-fcmpges=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1)
Integer id (N) of fcmpges custom instruction.
mno-custom-fcmpgts
Target RejectNegative Var(nios2_custom_fcmpgts, -1)
Do not use the fcmpgts custom instruction.
mcustom-fcmpgts=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1)
Integer id (N) of fcmpgts custom instruction.
mno-custom-fcmples
Target RejectNegative Var(nios2_custom_fcmples, -1)
Do not use the fcmples custom instruction.
mcustom-fcmples=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1)
Integer id (N) of fcmples custom instruction.
mno-custom-fcmplts
Target RejectNegative Var(nios2_custom_fcmplts, -1)
Do not use the fcmplts custom instruction.
mcustom-fcmplts=
Target RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1)
Integer id (N) of fcmplts custom instruction.
mno-custom-flogs
Target RejectNegative Var(nios2_custom_flogs, -1)
Do not use the flogs custom instruction.
mcustom-flogs=
Target RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1)
Integer id (N) of flogs custom instruction.
mno-custom-fexps
Target RejectNegative Var(nios2_custom_fexps, -1)
Do not use the fexps custom instruction.
mcustom-fexps=
Target RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1)
Integer id (N) of fexps custom instruction.
mno-custom-fatans
Target RejectNegative Var(nios2_custom_fatans, -1)
Do not use the fatans custom instruction.
mcustom-fatans=
Target RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1)
Integer id (N) of fatans custom instruction.
mno-custom-ftans
Target RejectNegative Var(nios2_custom_ftans, -1)
Do not use the ftans custom instruction.
mcustom-ftans=
Target RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1)
Integer id (N) of ftans custom instruction.
mno-custom-fsins
Target RejectNegative Var(nios2_custom_fsins, -1)
Do not use the fsins custom instruction.
mcustom-fsins=
Target RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1)
Integer id (N) of fsins custom instruction.
mno-custom-fcoss
Target RejectNegative Var(nios2_custom_fcoss, -1)
Do not use the fcoss custom instruction.
mcustom-fcoss=
Target RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1)
Integer id (N) of fcoss custom instruction.
mno-custom-fsqrts
Target RejectNegative Var(nios2_custom_fsqrts, -1)
Do not use the fsqrts custom instruction.
mcustom-fsqrts=
Target RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1)
Integer id (N) of fsqrts custom instruction.
mno-custom-fabss
Target RejectNegative Var(nios2_custom_fabss, -1)
Do not use the fabss custom instr.
mcustom-fabss=
Target RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1)
Integer id (N) of fabss custom instruction.
mno-custom-fnegs
Target RejectNegative Var(nios2_custom_fnegs, -1)
Do not use the fnegs custom instruction.
mcustom-fnegs=
Target RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1)
Integer id (N) of fnegs custom instruction.
mno-custom-fmaxs
Target RejectNegative Var(nios2_custom_fmaxs, -1)
Do not use the fmaxs custom instruction.
mcustom-fmaxs=
Target RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1)
Integer id (N) of fmaxs custom instruction.
mno-custom-fmins
Target RejectNegative Var(nios2_custom_fmins, -1)
Do not use the fmins custom instruction.
mcustom-fmins=
Target RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1)
Integer id (N) of fmins custom instruction.
mno-custom-fdivs
Target RejectNegative Var(nios2_custom_fdivs, -1)
Do not use the fdivs custom instruction.
mcustom-fdivs=
Target RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1)
Integer id (N) of fdivs custom instruction.
mno-custom-fmuls
Target RejectNegative Var(nios2_custom_fmuls, -1)
Do not use the fmuls custom instruction.
mcustom-fmuls=
Target RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1)
Integer id (N) of fmuls custom instruction.
mno-custom-fsubs
Target RejectNegative Var(nios2_custom_fsubs, -1)
Do not use the fsubs custom instruction.
mcustom-fsubs=
Target RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1)
Integer id (N) of fsubs custom instruction.
mno-custom-fadds
Target RejectNegative Var(nios2_custom_fadds, -1)
Do not use the fadds custom instruction.
mcustom-fadds=
Target RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1)
Integer id (N) of fadds custom instruction.
mno-custom-frdy
Target RejectNegative Var(nios2_custom_frdy, -1)
Do not use the frdy custom instruction.
mcustom-frdy=
Target RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1)
Integer id (N) of frdy custom instruction.
mno-custom-frdxhi
Target RejectNegative Var(nios2_custom_frdxhi, -1)
Do not use the frdxhi custom instruction.
mcustom-frdxhi=
Target RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1)
Integer id (N) of frdxhi custom instruction.
mno-custom-frdxlo
Target RejectNegative Var(nios2_custom_frdxlo, -1)
Do not use the frdxlo custom instruction.
mcustom-frdxlo=
Target RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1)
Integer id (N) of frdxlo custom instruction.
mno-custom-fwry
Target RejectNegative Var(nios2_custom_fwry, -1)
Do not use the fwry custom instruction.
mcustom-fwry=
Target RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1)
Integer id (N) of fwry custom instruction.
mno-custom-fwrx
Target RejectNegative Var(nios2_custom_fwrx, -1)
Do not use the fwrx custom instruction.
mcustom-fwrx=
Target RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1)
Integer id (N) of fwrx custom instruction.
mno-custom-round
Target RejectNegative Var(nios2_custom_round, -1)
Do not use the round custom instruction.
mcustom-round=
Target RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1)
Integer id (N) of round custom instruction.
march=
Target RejectNegative Joined Enum(nios2_arch_type) Var(nios2_arch_option) Init(ARCH_R1)
Specify the name of the target architecture.
Enum
Name(nios2_arch_type) Type(enum nios2_arch_type)
Valid Nios II ISA levels (for -march):
EnumValue
Enum(nios2_arch_type) String(r1) Value(ARCH_R1)
EnumValue
Enum(nios2_arch_type) String(r2) Value(ARCH_R2)
mbmx
Target Mask(HAS_BMX)
Enable generation of R2 BMX instructions.
mcdx
Target Mask(HAS_CDX)
Enable generation of R2 CDX instructions.
mgprel-sec=
Target RejectNegative Joined Var(nios2_gprel_sec) Init(NULL)
Regular expression matching additional GP-addressible section names.
mr0rel-sec=
Target RejectNegative Joined Var(nios2_r0rel_sec) Init(NULL)
Regular expression matching section names for r0-relative addressing.

50
gcc/config/nios2/nios2.opt.urls
View File

@@ -1,50 +0,0 @@
; Autogenerated by regenerate-opt-urls.py from gcc/config/nios2/nios2.opt and generated HTML
mhw-div
UrlSuffix(gcc/Nios-II-Options.html#index-mhw-div)
mhw-mul
UrlSuffix(gcc/Nios-II-Options.html#index-mhw-mul)
mhw-mulx
UrlSuffix(gcc/Nios-II-Options.html#index-mhw-mulx)
mfast-sw-div
UrlSuffix(gcc/Nios-II-Options.html#index-mfast-sw-div)
mbypass-cache
UrlSuffix(gcc/Nios-II-Options.html#index-mbypass-cache)
mno-cache-volatile
UrlSuffix(gcc/Nios-II-Options.html#index-mno-cache-volatile)
mcache-volatile
UrlSuffix(gcc/Nios-II-Options.html#index-mcache-volatile)
mgpopt=
UrlSuffix(gcc/Nios-II-Options.html#index-mgpopt-1)
mgpopt
UrlSuffix(gcc/Nios-II-Options.html#index-mgpopt-1)
mno-gpopt
UrlSuffix(gcc/Nios-II-Options.html#index-mno-gpopt-1)
meb
UrlSuffix(gcc/Nios-II-Options.html#index-meb-1)
mel
UrlSuffix(gcc/Nios-II-Options.html#index-mel-1)
mcustom-fpu-cfg=
UrlSuffix(gcc/Nios-II-Options.html#index-mcustom-fpu-cfg)
march=
UrlSuffix(gcc/Nios-II-Options.html#index-march-11)
mgprel-sec=
UrlSuffix(gcc/Nios-II-Options.html#index-mgprel-sec)
mr0rel-sec=
UrlSuffix(gcc/Nios-II-Options.html#index-mr0rel-sec)

161
gcc/config/nios2/predicates.md
View File

@@ -1,161 +0,0 @@
;; Predicate definitions for Altera Nios II.
;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
;; Contributed by Chung-Lin Tang <cltang@codesourcery.com>
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_predicate "const_0_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST0_RTX (GET_MODE (op))")))
(define_predicate "reg_or_0_operand"
(ior (match_operand 0 "const_0_operand")
(match_operand 0 "register_operand")))
(define_predicate "const_uns_arith_operand"
(and (match_code "const_int")
(match_test "SMALL_INT_UNSIGNED (INTVAL (op))")))
(define_predicate "uns_arith_operand"
(ior (match_operand 0 "const_uns_arith_operand")
(match_operand 0 "register_operand")))
(define_predicate "const_arith_operand"
(and (match_code "const_int")
(match_test "SMALL_INT (INTVAL (op))")))
(define_predicate "arith_operand"
(ior (match_operand 0 "const_arith_operand")
(match_operand 0 "register_operand")))
(define_predicate "add_regimm_operand"
(ior (match_operand 0 "arith_operand")
(match_test "nios2_unspec_reloc_p (op)")))
(define_predicate "const_logical_operand"
(and (match_code "const_int")
(match_test "(INTVAL (op) & 0xffff) == 0
|| (INTVAL (op) & 0xffff0000) == 0")))
(define_predicate "logical_operand"
(ior (match_operand 0 "const_logical_operand")
(match_operand 0 "register_operand")))
(define_predicate "const_and_operand"
(and (match_code "const_int")
(match_test "SMALL_INT_UNSIGNED (INTVAL (op))
|| UPPER16_INT (INTVAL (op))
|| (TARGET_ARCH_R2 && ANDCLEAR_INT (INTVAL (op)))")))
(define_predicate "and_operand"
(ior (match_operand 0 "const_and_operand")
(match_operand 0 "register_operand")))
(define_predicate "const_shift_operand"
(and (match_code "const_int")
(match_test "SHIFT_INT (INTVAL (op))")))
(define_predicate "shift_operand"
(ior (match_operand 0 "const_shift_operand")
(match_operand 0 "register_operand")))
(define_predicate "call_operand"
(ior (match_operand 0 "immediate_operand")
(match_operand 0 "register_operand")))
(define_predicate "rdwrctl_operand"
(and (match_code "const_int")
(match_test "RDWRCTL_INT (INTVAL (op))")))
(define_predicate "rdprs_dcache_operand"
(and (match_code "const_int")
(if_then_else (match_test "TARGET_ARCH_R2")
(match_test "SMALL_INT12 (INTVAL (op))")
(match_test "SMALL_INT (INTVAL (op))"))))
(define_predicate "custom_insn_opcode"
(and (match_code "const_int")
(match_test "CUSTOM_INSN_OPCODE (INTVAL (op))")))
(define_special_predicate "expandable_comparison_operator"
(match_operand 0 "ordered_comparison_operator")
{
return (GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) != MODE_FLOAT
|| nios2_validate_fpu_compare (GET_MODE (XEXP (op, 0)), &op,
&XEXP (op, 0), &XEXP (op, 1),
false));
})
(define_special_predicate "pop_operation"
(match_code "parallel")
{
return pop_operation_p (op);
})
(define_special_predicate "ldwm_operation"
(match_code "parallel")
{
return ldstwm_operation_p (op, /*load_p=*/true);
})
(define_special_predicate "stwm_operation"
(match_code "parallel")
{
return ldstwm_operation_p (op, /*load_p=*/false);
})
(define_predicate "nios2_hard_register_operand"
(match_code "reg")
{
return GP_REG_P (REGNO (op));
})
(define_predicate "stack_memory_operand"
(match_code "mem")
{
rtx addr = XEXP (op, 0);
return ((REG_P (addr) && REGNO (addr) == SP_REGNO)
|| (GET_CODE (addr) == PLUS
&& REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == SP_REGNO
&& CONST_INT_P (XEXP (addr, 1))));
})
(define_predicate "ldstio_memory_operand"
(match_code "mem")
{
if (TARGET_ARCH_R2)
{
rtx addr = XEXP (op, 0);
if (REG_P (addr))
return true;
else if (GET_CODE (addr) == PLUS)
return (REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1))
&& SMALL_INT12 (INTVAL (XEXP (addr, 1))));
else if (CONST_INT_P (addr))
return SMALL_INT12 (INTVAL (addr));
return false;
}
return memory_operand (op, mode);
})
(define_predicate "ldstex_memory_operand"
(match_code "mem")
{
/* ldex/ldsex/stex/stsex cannot handle memory addresses with offsets. */
return GET_CODE (XEXP (op, 0)) == REG;
})

39
gcc/config/nios2/rtems.h
View File

@@ -1,39 +0,0 @@
/* Definitions for rtems targeting a NIOS2 using ELF.
Copyright (C) 2011-2024 Free Software Foundation, Inc.
Contributed by Chris Johns (chrisj@rtems.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Specify predefined symbols in preprocessor. */
#define TARGET_OS_CPP_BUILTINS() \
do { \
builtin_define ("__rtems__"); \
builtin_define ("__USE_INIT_FINI__"); \
builtin_assert ("system=rtems"); \
} while (0)
/* This toolchain implements the ABI for Linux Systems documented in the
Nios II Processor Reference Handbook.
This is done so RTEMS targets have Thread Local Storage like Linux. */
#define TARGET_LINUX_ABI 1

45
gcc/config/nios2/sync.md
View File

@@ -1,45 +0,0 @@
;; Machine Description for Altera Nios II synchronization primitives.
;; Copyright (C) 2014-2024 Free Software Foundation, Inc.
;; Contributed by Mentor Graphics, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_int_iterator UNSPECV_LOAD_EXCLUSIVE [UNSPECV_LDEX UNSPECV_LDSEX])
(define_int_attr load_exclusive [(UNSPECV_LDEX "ldex")
(UNSPECV_LDSEX "ldsex")])
(define_insn "<load_exclusive>"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI
[(match_operand:SI 1 "ldstex_memory_operand" "v")]
UNSPECV_LOAD_EXCLUSIVE))]
"TARGET_ARCH_R2"
"<load_exclusive>\\t%0, %A1"
[(set_attr "type" "ld")])
(define_int_iterator UNSPECV_STORE_EXCLUSIVE [UNSPECV_STEX UNSPECV_STSEX])
(define_int_attr store_exclusive [(UNSPECV_STEX "stex")
(UNSPECV_STSEX "stsex")])
(define_insn "<store_exclusive>"
[(set (match_operand:SI 2 "register_operand" "=r")
(unspec_volatile:SI [(const_int 0)] UNSPECV_STORE_EXCLUSIVE))
(set (match_operand:SI 0 "ldstex_memory_operand" "=v")
(unspec_volatile:SI
[(match_operand:SI 1 "reg_or_0_operand" "rM")]
UNSPECV_STORE_EXCLUSIVE))]
"TARGET_ARCH_R2"
"<store_exclusive>\\t%2, %z1, %A0"
[(set_attr "type" "st")])

27
gcc/config/nios2/t-nios2
View File

@@ -1,27 +0,0 @@
# Target Makefile Fragment for Altera Nios II.
# Copyright (C) 2013-2024 Free Software Foundation, Inc.
# Contributed by Altera and Mentor Graphics, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published
# by the Free Software Foundation; either version 3, or (at your
# option) any later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# MULTILIB_OPTIONS = mno-hw-mul/mhw-mulx mcustom-fpu-cfg=60-1/mcustom-fpu-cfg=60-2
# MULTILIB_DIRNAMES = nomul mulx fpu-60-1 fpu-60-2
# MULTILIB_EXCEPTIONS =
# MULTILIB_OPTIONS += EL/EB
# MULTILIB_DIRNAMES += le be
# MULTILIB_MATCHES += EL=mel EB=meb

23
gcc/config/nios2/t-rtems
View File

@@ -1,23 +0,0 @@
# Custom RTEMS multilibs
# Reset all MULTILIB variables
MULTILIB_OPTIONS =
MULTILIB_DIRNAMES =
MULTILIB_EXCEPTIONS =
MULTILIB_REUSE =
MULTILIB_MATCHES =
MULTILIB_REQUIRED =
# Enumeration of multilibs
MULTILIB_OPTIONS += mhw-mul mhw-mulx mhw-div
MULTILIB_DIRNAMES += mul mulx div
MULTILIB_OPTIONS += mcustom-fadds=253 mcustom-fdivs=255 mcustom-fmuls=252 mcustom-fsubs=254 mcustom-fpu-cfg=fph2
MULTILIB_DIRNAMES += fadds fdivs fmuls fsubs fph2
MULTILIB_REQUIRED += mhw-mul
MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div
MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div/mcustom-fpu-cfg=fph2

44
gcc/configure vendored
View File

@@ -27497,11 +27497,6 @@ foo:
move.l x@TLSLE(%a5),%a0'
tls_as_opt='--fatal-warnings'
;;
nios2-*-*)
conftest_s='
.section ".tdata","awT",@progbits'
tls_as_opt="--fatal-warnings"
;;
aarch64*-*-*)
conftest_s='
.section ".tdata","awT",%progbits
@@ -30776,43 +30771,6 @@ $as_echo "#define HAVE_NEWLIB_NANO_FORMATTED_IO 1" >>confdefs.h
fi
;;
nios2-*-*)
# Versions 2.33 and earlier lacked support for the %gotoff relocation
# syntax that is documented in the ABI specification.
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for support for %gotoff relocations in constant data" >&5
$as_echo_n "checking assembler for support for %gotoff relocations in constant data... " >&6; }
if ${gcc_cv_as_nios2_gotoff_relocation+:} false; then :
$as_echo_n "(cached) " >&6
else
gcc_cv_as_nios2_gotoff_relocation=no
if test x$gcc_cv_as != x; then
$as_echo ' .extern foo
.data
.long %gotoff(foo)' > conftest.s
if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5'
{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
(eval $ac_try) 2>&5
ac_status=$?
$as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
test $ac_status = 0; }; }
then
gcc_cv_as_nios2_gotoff_relocation=yes
else
echo "configure: failed program was" >&5
cat conftest.s >&5
fi
rm -f conftest.o conftest.s
fi
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_nios2_gotoff_relocation" >&5
$as_echo "$gcc_cv_as_nios2_gotoff_relocation" >&6; }
if test $gcc_cv_as_nios2_gotoff_relocation = yes; then
$as_echo "#define HAVE_AS_NIOS2_GOTOFF_RELOCATION 1" >>confdefs.h
fi
;;
riscv*-*-*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .attribute support" >&5
$as_echo_n "checking assembler for .attribute support... " >&6; }
@@ -31451,7 +31409,7 @@ esac
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | m32c \
| m68k | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
| m68k | microblaze | mips | nds32 | pa | riscv | rs6000 | score | sparc \
| visium | xstormy16 | xtensa | ft32)
insn="nop"
;;

18
gcc/configure.ac
View File

@@ -3952,11 +3952,6 @@ foo:
move.l x@TLSLE(%a5),%a0'
tls_as_opt='--fatal-warnings'
;;
nios2-*-*)
conftest_s='
.section ".tdata","awT",@progbits'
tls_as_opt="--fatal-warnings"
;;
aarch64*-*-*)
conftest_s='
.section ".tdata","awT",%progbits
@@ -5438,17 +5433,6 @@ pointers into PC-relative form.])
configured with --enable-newlib-nano-formatted-io.])
fi
;;
nios2-*-*)
# Versions 2.33 and earlier lacked support for the %gotoff relocation
# syntax that is documented in the ABI specification.
gcc_GAS_CHECK_FEATURE([support for %gotoff relocations in constant data],
gcc_cv_as_nios2_gotoff_relocation,,
[ .extern foo
.data
.long %gotoff(foo)],,
[AC_DEFINE(HAVE_AS_NIOS2_GOTOFF_RELOCATION, 1,
[Define if your assembler supports %gotoff relocation syntax.])])
;;
riscv*-*-*)
gcc_GAS_CHECK_FEATURE([.attribute support],
gcc_cv_as_riscv_attribute,,
@@ -5618,7 +5602,7 @@ esac
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | loongarch | m32c \
| m68k | microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
| m68k | microblaze | mips | nds32 | pa | riscv | rs6000 | score | sparc \
| visium | xstormy16 | xtensa | ft32)
insn="nop"
;;

156
gcc/doc/extend.texi
View File

@@ -2641,7 +2641,6 @@ GCC plugins may provide their own attributes.
* MIPS Function Attributes::
* MSP430 Function Attributes::
* NDS32 Function Attributes::
* Nios II Function Attributes::
* Nvidia PTX Function Attributes::
* PowerPC Function Attributes::
* RISC-V Function Attributes::
@@ -4312,8 +4311,7 @@ within the strings.
The options supported are specific to each target; refer to @ref{x86
Function Attributes}, @ref{PowerPC Function Attributes},
@ref{ARM Function Attributes}, @ref{AArch64 Function Attributes},
@ref{Nios II Function Attributes}, and @ref{S/390 Function Attributes}
for details.
and @ref{S/390 Function Attributes} for details.
@cindex @code{target_clones} function attribute
@item target_clones (@var{options})
@@ -6193,42 +6191,6 @@ Provide a user-defined function to handle warm reset exception.
@end table
@end table
@node Nios II Function Attributes
@subsection Nios II Function Attributes
These function attributes are supported by the Nios II back end:
@table @code
@cindex @code{target} function attribute
@item target (@var{options})
As discussed in @ref{Common Function Attributes}, this attribute
allows specification of target-specific compilation options.
When compiling for Nios II, the following options are allowed:
@table @samp
@cindex @code{target("custom-@var{insn}=@var{N}")} function attribute, Nios II
@cindex @code{target("no-custom-@var{insn}")} function attribute, Nios II
@item custom-@var{insn}=@var{N}
@itemx no-custom-@var{insn}
Each @samp{custom-@var{insn}=@var{N}} attribute locally enables use of a
custom instruction with encoding @var{N} when generating code that uses
@var{insn}. Similarly, @samp{no-custom-@var{insn}} locally inhibits use of
the custom instruction @var{insn}.
These target attributes correspond to the
@option{-mcustom-@var{insn}=@var{N}} and @option{-mno-custom-@var{insn}}
command-line options, and support the same set of @var{insn} keywords.
@xref{Nios II Options}, for more information.
@cindex @code{target("custom-fpu-cfg=@var{name}")} function attribute, Nios II
@item custom-fpu-cfg=@var{name}
This attribute corresponds to the @option{-mcustom-fpu-cfg=@var{name}}
command-line option, to select a predefined set of custom instructions
named @var{name}.
@xref{Nios II Options}, for more information.
@end table
@end table
@node Nvidia PTX Function Attributes
@subsection Nvidia PTX Function Attributes
@@ -16292,7 +16254,6 @@ instructions, but allow the compiler to schedule those calls.
@menu
* AArch64 Built-in Functions::
* Alpha Built-in Functions::
* Altera Nios II Built-in Functions::
* ARC Built-in Functions::
* ARC SIMD Built-in Functions::
* ARM iWMMXt Built-in Functions::
@@ -16432,119 +16393,6 @@ void *__builtin_thread_pointer (void);
void __builtin_set_thread_pointer (void *);
@end smallexample
@node Altera Nios II Built-in Functions
@subsection Altera Nios II Built-in Functions
These built-in functions are available for the Altera Nios II
family of processors.
The following built-in functions are always available. They
all generate the machine instruction that is part of the name.
@example
int __builtin_ldbio (volatile const void *);
int __builtin_ldbuio (volatile const void *);
int __builtin_ldhio (volatile const void *);
int __builtin_ldhuio (volatile const void *);
int __builtin_ldwio (volatile const void *);
void __builtin_stbio (volatile void *, int);
void __builtin_sthio (volatile void *, int);
void __builtin_stwio (volatile void *, int);
void __builtin_sync (void);
int __builtin_rdctl (int);
int __builtin_rdprs (int, int);
void __builtin_wrctl (int, int);
void __builtin_flushd (volatile void *);
void __builtin_flushda (volatile void *);
int __builtin_wrpie (int);
void __builtin_eni (int);
int __builtin_ldex (volatile const void *);
int __builtin_stex (volatile void *, int);
int __builtin_ldsex (volatile const void *);
int __builtin_stsex (volatile void *, int);
@end example
The following built-in functions are always available. They
all generate a Nios II Custom Instruction. The name of the
function represents the types that the function takes and
returns. The letter before the @code{n} is the return type
or void if absent. The @code{n} represents the first parameter
to all the custom instructions, the custom instruction number.
The two letters after the @code{n} represent the up to two
parameters to the function.
The letters represent the following data types:
@table @code
@item <no letter>
@code{void} for return type and no parameter for parameter types.
@item i
@code{int} for return type and parameter type
@item f
@code{float} for return type and parameter type
@item p
@code{void *} for return type and parameter type
@end table
And the function names are:
@example
void __builtin_custom_n (void);
void __builtin_custom_ni (int);
void __builtin_custom_nf (float);
void __builtin_custom_np (void *);
void __builtin_custom_nii (int, int);
void __builtin_custom_nif (int, float);
void __builtin_custom_nip (int, void *);
void __builtin_custom_nfi (float, int);
void __builtin_custom_nff (float, float);
void __builtin_custom_nfp (float, void *);
void __builtin_custom_npi (void *, int);
void __builtin_custom_npf (void *, float);
void __builtin_custom_npp (void *, void *);
int __builtin_custom_in (void);
int __builtin_custom_ini (int);
int __builtin_custom_inf (float);
int __builtin_custom_inp (void *);
int __builtin_custom_inii (int, int);
int __builtin_custom_inif (int, float);
int __builtin_custom_inip (int, void *);
int __builtin_custom_infi (float, int);
int __builtin_custom_inff (float, float);
int __builtin_custom_infp (float, void *);
int __builtin_custom_inpi (void *, int);
int __builtin_custom_inpf (void *, float);
int __builtin_custom_inpp (void *, void *);
float __builtin_custom_fn (void);
float __builtin_custom_fni (int);
float __builtin_custom_fnf (float);
float __builtin_custom_fnp (void *);
float __builtin_custom_fnii (int, int);
float __builtin_custom_fnif (int, float);
float __builtin_custom_fnip (int, void *);
float __builtin_custom_fnfi (float, int);
float __builtin_custom_fnff (float, float);
float __builtin_custom_fnfp (float, void *);
float __builtin_custom_fnpi (void *, int);
float __builtin_custom_fnpf (void *, float);
float __builtin_custom_fnpp (void *, void *);
void * __builtin_custom_pn (void);
void * __builtin_custom_pni (int);
void * __builtin_custom_pnf (float);
void * __builtin_custom_pnp (void *);
void * __builtin_custom_pnii (int, int);
void * __builtin_custom_pnif (int, float);
void * __builtin_custom_pnip (int, void *);
void * __builtin_custom_pnfi (float, int);
void * __builtin_custom_pnff (float, float);
void * __builtin_custom_pnfp (float, void *);
void * __builtin_custom_pnpi (void *, int);
void * __builtin_custom_pnpf (void *, float);
void * __builtin_custom_pnpp (void *, void *);
@end example
@node ARC Built-in Functions
@subsection ARC Built-in Functions
@@ -28884,7 +28732,7 @@ for more information about the @code{target} attribute and the attribute
syntax.
The @code{#pragma GCC target} pragma is presently implemented for
x86, ARM, AArch64, PowerPC, S/390, and Nios II targets only.
x86, ARM, AArch64, PowerPC, and S/390 targets only.
@cindex pragma GCC optimize
@item #pragma GCC optimize (@var{string}, @dots{})

2
gcc/doc/install.texi
View File

@@ -833,7 +833,7 @@ hppa64, i486, i686, ia64, iq2000, lm32, loongarch64, m32c, m32r, m32rle, m68k,
mcore, microblaze, microblazeel, mips, mips64, mips64el, mips64octeon,
mips64orion, mips64vr, mipsel, mipsisa32, mipsisa32r2, mipsisa64, mipsisa64r2,
mipsisa64r2el, mipsisa64sb1, mipsisa64sr71k, mipstx39, mmix, mn10300, moxie,
msp430, nds32be, nds32le, nios2, nvptx, or1k, pdp11, powerpc, powerpc64,
msp430, nds32be, nds32le, nvptx, or1k, pdp11, powerpc, powerpc64,
powerpc64le, powerpcle, pru, riscv32, riscv32be, riscv64, riscv64be, rl78, rx,
s390, s390x, sh, shle, sparc, sparc64, tic6x, v850,
v850e, v850e1, vax, visium, x86_64, xstormy16, xtensa

415
gcc/doc/invoke.texi
View File

@@ -1218,19 +1218,6 @@ Objective-C and Objective-C++ Dialects}.
-mcmodel=@var{code-model}
-mctor-dtor -mrelax}
@emph{Nios II Options}
@gccoptlist{-G @var{num} -mgpopt=@var{option} -mgpopt -mno-gpopt
-mgprel-sec=@var{regexp} -mr0rel-sec=@var{regexp}
-mel -meb
-mno-bypass-cache -mbypass-cache
-mno-cache-volatile -mcache-volatile
-mno-fast-sw-div -mfast-sw-div
-mhw-mul -mno-hw-mul -mhw-mulx -mno-hw-mulx -mno-hw-div -mhw-div
-mcustom-@var{insn}=@var{N} -mno-custom-@var{insn}
-mcustom-fpu-cfg=@var{name}
-mhal -msmallc -msys-crt0=@var{name} -msys-lib=@var{name}
-march=@var{arch} -mbmx -mno-bmx -mcdx -mno-cdx}
@emph{Nvidia PTX Options}
@gccoptlist{-m64 -mmainkernel -moptimize}
@@ -13267,8 +13254,8 @@ Note however that in some environments this assumption is not true.
Use @option{-fno-delete-null-pointer-checks} to disable this optimization
for programs that depend on that behavior.
This option is enabled by default on most targets. On Nios II ELF, it
defaults to off. On AVR and MSP430, this option is completely disabled.
This option is enabled by default on most targets.
On AVR and MSP430, this option is completely disabled.
Passes that use the dataflow information
are enabled independently at different optimization levels.
@@ -21314,7 +21301,6 @@ platform.
* Moxie Options::
* MSP430 Options::
* NDS32 Options::
* Nios II Options::
* Nvidia PTX Options::
* OpenRISC Options::
* PDP-11 Options::
@@ -29916,403 +29902,6 @@ Guide linker to relax instructions.
@end table
@node Nios II Options
@subsection Nios II Options
@cindex Nios II options
@cindex Altera Nios II options
These are the options defined for the Altera Nios II processor.
@table @gcctabopt
@opindex G
@cindex smaller data references
@item -G @var{num}
Put global and static objects less than or equal to @var{num} bytes
into the small data or BSS sections instead of the normal data or BSS
sections. The default value of @var{num} is 8.
@opindex mgpopt
@opindex mno-gpopt
@item -mgpopt=@var{option}
@itemx -mgpopt
@itemx -mno-gpopt
Generate (do not generate) GP-relative accesses. The following
@var{option} names are recognized:
@table @samp
@item none
Do not generate GP-relative accesses.
@item local
Generate GP-relative accesses for small data objects that are not
external, weak, or uninitialized common symbols.
Also use GP-relative addressing for objects that
have been explicitly placed in a small data section via a @code{section}
attribute.
@item global
As for @samp{local}, but also generate GP-relative accesses for
small data objects that are external, weak, or common. If you use this option,
you must ensure that all parts of your program (including libraries) are
compiled with the same @option{-G} setting.
@item data
Generate GP-relative accesses for all data objects in the program. If you
use this option, the entire data and BSS segments
of your program must fit in 64K of memory and you must use an appropriate
linker script to allocate them within the addressable range of the
global pointer.
@item all
Generate GP-relative addresses for function pointers as well as data
pointers. If you use this option, the entire text, data, and BSS segments
of your program must fit in 64K of memory and you must use an appropriate
linker script to allocate them within the addressable range of the
global pointer.
@end table
@option{-mgpopt} is equivalent to @option{-mgpopt=local}, and
@option{-mno-gpopt} is equivalent to @option{-mgpopt=none}.
The default is @option{-mgpopt} except when @option{-fpic} or
@option{-fPIC} is specified to generate position-independent code.
Note that the Nios II ABI does not permit GP-relative accesses from
shared libraries.
You may need to specify @option{-mno-gpopt} explicitly when building
programs that include large amounts of small data, including large
GOT data sections. In this case, the 16-bit offset for GP-relative
addressing may not be large enough to allow access to the entire
small data section.
@opindex mgprel-sec
@item -mgprel-sec=@var{regexp}
This option specifies additional section names that can be accessed via
GP-relative addressing. It is most useful in conjunction with
@code{section} attributes on variable declarations
(@pxref{Common Variable Attributes}) and a custom linker script.
The @var{regexp} is a POSIX Extended Regular Expression.
This option does not affect the behavior of the @option{-G} option, and
the specified sections are in addition to the standard @code{.sdata}
and @code{.sbss} small-data sections that are recognized by @option{-mgpopt}.
@opindex mr0rel-sec
@item -mr0rel-sec=@var{regexp}
This option specifies names of sections that can be accessed via a
16-bit offset from @code{r0}; that is, in the low 32K or high 32K
of the 32-bit address space. It is most useful in conjunction with
@code{section} attributes on variable declarations
(@pxref{Common Variable Attributes}) and a custom linker script.
The @var{regexp} is a POSIX Extended Regular Expression.
In contrast to the use of GP-relative addressing for small data,
zero-based addressing is never generated by default and there are no
conventional section names used in standard linker scripts for sections
in the low or high areas of memory.
@opindex mel
@opindex meb
@item -mel
@itemx -meb
Generate little-endian (default) or big-endian (experimental) code,
respectively.
@opindex march
@item -march=@var{arch}
This specifies the name of the target Nios II architecture. GCC uses this
name to determine what kind of instructions it can emit when generating
assembly code. Permissible names are: @samp{r1}, @samp{r2}.
The preprocessor macro @code{__nios2_arch__} is available to programs,
with value 1 or 2, indicating the targeted ISA level.
@opindex mno-bypass-cache
@opindex mbypass-cache
@item -mbypass-cache
@itemx -mno-bypass-cache
Force all load and store instructions to always bypass cache by
using I/O variants of the instructions. The default is not to
bypass the cache.
@opindex mcache-volatile
@opindex mno-cache-volatile
@item -mno-cache-volatile
@itemx -mcache-volatile
Volatile memory access bypass the cache using the I/O variants of
the load and store instructions. The default is not to bypass the cache.
@opindex mno-fast-sw-div
@opindex mfast-sw-div
@item -mno-fast-sw-div
@itemx -mfast-sw-div
Do not use table-based fast divide for small numbers. The default
is to use the fast divide at @option{-O3} and above.
@opindex mno-hw-mul
@opindex mhw-mul
@opindex mno-hw-mulx
@opindex mhw-mulx
@opindex mno-hw-div
@opindex mhw-div
@item -mno-hw-mul
@itemx -mhw-mul
@itemx -mno-hw-mulx
@itemx -mhw-mulx
@itemx -mno-hw-div
@itemx -mhw-div
Enable or disable emitting @code{mul}, @code{mulx} and @code{div} family of
instructions by the compiler. The default is to emit @code{mul}
and not emit @code{div} and @code{mulx}.
@item -mbmx
@itemx -mno-bmx
@itemx -mcdx
@itemx -mno-cdx
Enable or disable generation of Nios II R2 BMX (bit manipulation) and
CDX (code density) instructions. Enabling these instructions also
requires @option{-march=r2}. Since these instructions are optional
extensions to the R2 architecture, the default is not to emit them.
@opindex mcustom-@var{insn}
@opindex mno-custom-@var{insn}
@item -mcustom-@var{insn}=@var{N}
@itemx -mno-custom-@var{insn}
Each @option{-mcustom-@var{insn}=@var{N}} option enables use of a
custom instruction with encoding @var{N} when generating code that uses
@var{insn}. For example, @option{-mcustom-fadds=253} generates custom
instruction 253 for single-precision floating-point add operations instead
of the default behavior of using a library call.
The following values of @var{insn} are supported. Except as otherwise
noted, floating-point operations are expected to be implemented with
normal IEEE 754 semantics and correspond directly to the C operators or the
equivalent GCC built-in functions (@pxref{Other Builtins}).
Single-precision floating point:
@table @asis
@item @samp{fadds}, @samp{fsubs}, @samp{fdivs}, @samp{fmuls}
Binary arithmetic operations.
@item @samp{fnegs}
Unary negation.
@item @samp{fabss}
Unary absolute value.
@item @samp{fcmpeqs}, @samp{fcmpges}, @samp{fcmpgts}, @samp{fcmples}, @samp{fcmplts}, @samp{fcmpnes}
Comparison operations.
@item @samp{fmins}, @samp{fmaxs}
Floating-point minimum and maximum. These instructions are only
generated if @option{-ffinite-math-only} is specified.
@item @samp{fsqrts}
Unary square root operation.
@item @samp{fcoss}, @samp{fsins}, @samp{ftans}, @samp{fatans}, @samp{fexps}, @samp{flogs}
Floating-point trigonometric and exponential functions. These instructions
are only generated if @option{-funsafe-math-optimizations} is also specified.
@end table
Double-precision floating point:
@table @asis
@item @samp{faddd}, @samp{fsubd}, @samp{fdivd}, @samp{fmuld}
Binary arithmetic operations.
@item @samp{fnegd}
Unary negation.
@item @samp{fabsd}
Unary absolute value.
@item @samp{fcmpeqd}, @samp{fcmpged}, @samp{fcmpgtd}, @samp{fcmpled}, @samp{fcmpltd}, @samp{fcmpned}
Comparison operations.
@item @samp{fmind}, @samp{fmaxd}
Double-precision minimum and maximum. These instructions are only
generated if @option{-ffinite-math-only} is specified.
@item @samp{fsqrtd}
Unary square root operation.
@item @samp{fcosd}, @samp{fsind}, @samp{ftand}, @samp{fatand}, @samp{fexpd}, @samp{flogd}
Double-precision trigonometric and exponential functions. These instructions
are only generated if @option{-funsafe-math-optimizations} is also specified.
@end table
Conversions:
@table @asis
@item @samp{fextsd}
Conversion from single precision to double precision.
@item @samp{ftruncds}
Conversion from double precision to single precision.
@item @samp{fixsi}, @samp{fixsu}, @samp{fixdi}, @samp{fixdu}
Conversion from floating point to signed or unsigned integer types, with
truncation towards zero.
@item @samp{round}
Conversion from single-precision floating point to signed integer,
rounding to the nearest integer and ties away from zero.
This corresponds to the @code{__builtin_lroundf} function when
@option{-fno-math-errno} is used.
@item @samp{floatis}, @samp{floatus}, @samp{floatid}, @samp{floatud}
Conversion from signed or unsigned integer types to floating-point types.
@end table
In addition, all of the following transfer instructions for internal
registers X and Y must be provided to use any of the double-precision
floating-point instructions. Custom instructions taking two
double-precision source operands expect the first operand in the
64-bit register X. The other operand (or only operand of a unary
operation) is given to the custom arithmetic instruction with the
least significant half in source register @var{src1} and the most
significant half in @var{src2}. A custom instruction that returns a
double-precision result returns the most significant 32 bits in the
destination register and the other half in 32-bit register Y.
GCC automatically generates the necessary code sequences to write
register X and/or read register Y when double-precision floating-point
instructions are used.
@table @asis
@item @samp{fwrx}
Write @var{src1} into the least significant half of X and @var{src2} into
the most significant half of X.
@item @samp{fwry}
Write @var{src1} into Y.
@item @samp{frdxhi}, @samp{frdxlo}
Read the most or least (respectively) significant half of X and store it in
@var{dest}.
@item @samp{frdy}
Read the value of Y and store it into @var{dest}.
@end table
Note that you can gain more local control over generation of Nios II custom
instructions by using the @code{target("custom-@var{insn}=@var{N}")}
and @code{target("no-custom-@var{insn}")} function attributes
(@pxref{Function Attributes})
or pragmas (@pxref{Function Specific Option Pragmas}).
@opindex mcustom-fpu-cfg
@item -mcustom-fpu-cfg=@var{name}
This option enables a predefined, named set of custom instruction encodings
(see @option{-mcustom-@var{insn}} above).
Currently, the following sets are defined:
@option{-mcustom-fpu-cfg=60-1} is equivalent to:
@gccoptlist{-mcustom-fmuls=252
-mcustom-fadds=253
-mcustom-fsubs=254
-fsingle-precision-constant}
@option{-mcustom-fpu-cfg=60-2} is equivalent to:
@gccoptlist{-mcustom-fmuls=252
-mcustom-fadds=253
-mcustom-fsubs=254
-mcustom-fdivs=255
-fsingle-precision-constant}
@option{-mcustom-fpu-cfg=72-3} is equivalent to:
@gccoptlist{-mcustom-floatus=243
-mcustom-fixsi=244
-mcustom-floatis=245
-mcustom-fcmpgts=246
-mcustom-fcmples=249
-mcustom-fcmpeqs=250
-mcustom-fcmpnes=251
-mcustom-fmuls=252
-mcustom-fadds=253
-mcustom-fsubs=254
-mcustom-fdivs=255
-fsingle-precision-constant}
@option{-mcustom-fpu-cfg=fph2} is equivalent to:
@gccoptlist{-mcustom-fabss=224
-mcustom-fnegs=225
-mcustom-fcmpnes=226
-mcustom-fcmpeqs=227
-mcustom-fcmpges=228
-mcustom-fcmpgts=229
-mcustom-fcmples=230
-mcustom-fcmplts=231
-mcustom-fmaxs=232
-mcustom-fmins=233
-mcustom-round=248
-mcustom-fixsi=249
-mcustom-floatis=250
-mcustom-fsqrts=251
-mcustom-fmuls=252
-mcustom-fadds=253
-mcustom-fsubs=254
-mcustom-fdivs=255}
Custom instruction assignments given by individual
@option{-mcustom-@var{insn}=} options override those given by
@option{-mcustom-fpu-cfg=}, regardless of the
order of the options on the command line.
Note that you can gain more local control over selection of a FPU
configuration by using the @code{target("custom-fpu-cfg=@var{name}")}
function attribute (@pxref{Function Attributes})
or pragma (@pxref{Function Specific Option Pragmas}).
The name @var{fph2} is an abbreviation for @emph{Nios II Floating Point
Hardware 2 Component}. Please note that the custom instructions enabled by
@option{-mcustom-fmins=233} and @option{-mcustom-fmaxs=234} are only generated
if @option{-ffinite-math-only} is specified. The custom instruction enabled by
@option{-mcustom-round=248} is only generated if @option{-fno-math-errno} is
specified. In contrast to the other configurations,
@option{-fsingle-precision-constant} is not set.
@end table
These additional @samp{-m} options are available for the Altera Nios II
ELF (bare-metal) target:
@table @gcctabopt
@opindex mhal
@item -mhal
Link with HAL BSP. This suppresses linking with the GCC-provided C runtime
startup and termination code, and is typically used in conjunction with
@option{-msys-crt0=} to specify the location of the alternate startup code
provided by the HAL BSP.
@opindex msmallc
@item -msmallc
Link with a limited version of the C library, @option{-lsmallc}, rather than
Newlib.
@opindex msys-crt0
@item -msys-crt0=@var{startfile}
@var{startfile} is the file name of the startfile (crt0) to use
when linking. This option is only useful in conjunction with @option{-mhal}.
@opindex msys-lib
@item -msys-lib=@var{systemlib}
@var{systemlib} is the library name of the library that provides
low-level system calls required by the C library,
e.g.@: @code{read} and @code{write}.
This option is typically used to link with a library provided by a HAL BSP.
@end table
@node Nvidia PTX Options
@subsection Nvidia PTX Options
@cindex Nvidia PTX options

61
gcc/doc/md.texi
View File

@@ -3218,67 +3218,6 @@ Memory constraint for 45 format.
Memory constraint for 37 format.
@end table
@item Nios II family---@file{config/nios2/constraints.md}
@table @code
@item I
Integer that is valid as an immediate operand in an
instruction taking a signed 16-bit number. Range
@minus{}32768 to 32767.
@item J
Integer that is valid as an immediate operand in an
instruction taking an unsigned 16-bit number. Range
0 to 65535.
@item K
Integer that is valid as an immediate operand in an
instruction taking only the upper 16-bits of a
32-bit number. Range 32-bit numbers with the lower
16-bits being 0.
@item L
Integer that is valid as an immediate operand for a
shift instruction. Range 0 to 31.
@item M
Integer that is valid as an immediate operand for
only the value 0. Can be used in conjunction with
the format modifier @code{z} to use @code{r0}
instead of @code{0} in the assembly output.
@item N
Integer that is valid as an immediate operand for
a custom instruction opcode. Range 0 to 255.
@item P
An immediate operand for R2 andchi/andci instructions.
@item S
Matches immediates which are addresses in the small
data section and therefore can be added to @code{gp}
as a 16-bit immediate to re-create their 32-bit value.
@item U
Matches constants suitable as an operand for the rdprs and
cache instructions.
@item v
A memory operand suitable for Nios II R2 load/store
exclusive instructions.
@item w
A memory operand suitable for load/store IO and cache
instructions.
@ifset INTERNALS
@item T
A @code{const} wrapped @code{UNSPEC} expression,
representing a supported PIC or TLS relocation.
@end ifset
@end table
@item OpenRISC---@file{config/or1k/constraints.md}
@table @code
@item I

1
gcc/regenerate-opt-urls.py
View File

@@ -248,7 +248,6 @@ TARGET_SPECIFIC_PAGES = {
'gcc/MicroBlaze-Options.html' : 'gcc/config/microblaze/',
'gcc/Moxie-Options.html' : 'gcc/config/moxie/',
'gcc/NDS32-Options.html' : 'gcc/config/nds32/',
'gcc/Nios-II-Options.html' : 'gcc/config/nios2/',
'gcc/Nvidia-PTX-Options.html' : 'gcc/config/nvptx/',
'gcc/OpenRISC-Options.html' : 'gcc/config/or1k/',
'gcc/PDP-11-Options.html' : 'gcc/config/pdp11',

2
gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
View File

@@ -1,6 +1,6 @@
// PR c++/49673: check that test_data goes into .rodata
// { dg-do compile { target c++11 } }
// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* loongarch*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* loongarch*-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
// { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } }
// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* *-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } }

2
gcc/testsuite/g++.old-deja/g++.jason/thunk3.C
View File

@@ -1,5 +1,5 @@
// { dg-do run }
// { dg-skip-if "fails with generic thunk support" { rs6000-*-* powerpc-*-eabi v850-*-* sh-*-* h8*-*-* xtensa*-*-* m32r*-*-* lm32-*-* nios2-*-* } }
// { dg-skip-if "fails with generic thunk support" { rs6000-*-* powerpc-*-eabi v850-*-* sh-*-* h8*-*-* xtensa*-*-* m32r*-*-* lm32-*-* } }
// Test that variadic function calls using thunks work right.
// Note that this will break on any target that uses the generic thunk
// support, because it doesn't support variadic functions.

14
gcc/testsuite/g++.target/nios2/hello-pie.C
View File

@@ -1,14 +0,0 @@
// { dg-do run { target *-*-linux* } }
// { dg-options "-pie -fpie" }
// { dg-output "Hello, pie World" }
// This test used to give an "FDE encoding" error from the linker due to
// the ABI not having appropriate relocations for PIE.
#include <iostream>
int
main ()
{
std::cout << "Hello, pie World" << std::endl;
}

34
gcc/testsuite/g++.target/nios2/nios2.exp
View File

@@ -1,34 +0,0 @@
# Copyright (C) 2019-2024 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# GCC testsuite that uses the `dg.exp' driver.
# Exit immediately if this isn't a nios2 target.
if ![istarget nios2*-*-*] then {
return
}
# Load support procs.
load_lib g++-dg.exp
# Initialize `dg'.
dg-init
# Main loop.
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] "" ""
# All done.
dg-finish

4
gcc/testsuite/gcc.c-torture/execute/20101011-1.c
View File

@@ -87,10 +87,6 @@ __aeabi_idiv0 (int return_value)
}
# define DO_TEST 1
# endif
#elif defined (__nios2__)
/* Nios II requires both hardware support and user configuration to
raise an exception on divide by zero. */
# define DO_TEST 0
#elif defined (__nvptx__)
/* There isn't even a signal function. */
# define DO_TEST 0

2
gcc/testsuite/gcc.c-torture/execute/pr47237.c
View File

@@ -1,4 +1,4 @@
/* { dg-xfail-run-if "can cause stack underflow" { nios2-*-* amdgcn-*-* } } */
/* { dg-xfail-run-if "can cause stack underflow" { amdgcn-*-* } } */
/* { dg-require-effective-target untyped_assembly } */
#define INTEGER_ARG 5

2
gcc/testsuite/gcc.dg/20020312-2.c
View File

@@ -59,8 +59,6 @@ extern void abort (void);
/* No pic register. */
#elif defined(__nds32__)
/* No pic register. */
#elif defined(__nios2__)
/* No pic register. */
#elif defined(__hppa__)
/* PIC register is %r27 or %r19, but is used even without -fpic. */
#elif defined(__pdp11__)

1
gcc/testsuite/gcc.dg/20021029-1.c
View File

@@ -2,7 +2,6 @@
variables into writable sections. */
/* { dg-do compile { target fpic } } */
/* { dg-options "-O2 -fpic" } */
/* { dg-additional-options "-G0" { target nios2-*-* } } */
/* { dg-final { scan-assembler-not ".data.rel.ro.local" } } */
/* { dg-final { scan-assembler-symbol-section {^_?ar} {^\.(const|rodata)|\[RO\]} } } */
/* { dg-require-effective-target label_values } */

1
gcc/testsuite/gcc.dg/debug/btf/btf-datasec-1.c
View File

@@ -13,7 +13,6 @@
/* { dg-options "-O0 -gbtf -dA" } */
/* { dg-additional-options "-msdata=none" { target { { powerpc*-*-* } && ilp32 } } } */
/* { dg-additional-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */
/* { dg-additional-options "-G0" { target { nios2-*-* } } } */
/* Check for two DATASEC entries with vlen 3, and one with vlen 1. */
/* { dg-final { scan-assembler-times "0xf000003\[\t \]+\[^\n\]*btt_info" 2 } } */

2
gcc/testsuite/gcc.dg/ifcvt-4.c
View File

@@ -2,7 +2,7 @@
/* { dg-additional-options "-misel" { target { powerpc*-*-* } } } */
/* { dg-additional-options "-march=z196" { target { s390x-*-* } } } */
/* { dg-additional-options "-mtune-ctrl=^one_if_conv_insn" { target { i?86-*-* x86_64-*-* } } } */
/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" { "arm*-*-* avr-*-* cris-*-* hppa*64*-*-* visium-*-*" riscv*-*-* msp430-*-* nios2-*-* pru-*-* } } */
/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" { "arm*-*-* avr-*-* cris-*-* hppa*64*-*-* visium-*-*" riscv*-*-* msp430-*-* pru-*-* } } */
/* { dg-skip-if "" { { sparc*-*-* } && { ! sparc_v9 } } } */
/* { dg-skip-if "" { "s390x-*-*" } { "-m31" } } */

2
gcc/testsuite/gcc.dg/stack-usage-1.c
View File

@@ -89,8 +89,6 @@
# define SIZE 248
#elif defined (xstormy16)
# define SIZE 254
#elif defined (__nios2__)
# define SIZE 252
#elif defined (__PRU__)
# define SIZE 252
#elif defined (__v850__)

1
gcc/testsuite/gcc.dg/struct-by-value-1.c
View File

@@ -1,7 +1,6 @@
/* Test structure passing by value. */
/* { dg-do run } */
/* { dg-options "-O2" } */
/* { dg-options "-O2 -G0" { target { nios2-*-* } } } */
#define T(N) \
struct S##N { unsigned char i[N]; }; \

2
gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c
View File

@@ -1,4 +1,4 @@
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k-*-*-* pru*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k-*-*-* pru*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1" } */
/* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

2
gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c
View File

@@ -1,4 +1,4 @@
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k*-*-* pru*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1" } */
/* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

2
gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c
View File

@@ -1,4 +1,4 @@
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k*-*-* pru*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1" } */
/* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

2
gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c
View File

@@ -1,4 +1,4 @@
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* or1k*-*-* pru*-*-*"} } } */
/* { dg-do run { target { ! "m68k*-*-* mmix*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* or1k*-*-* pru*-*-*"} } } */
/* { dg-options "-O2 -fno-inline -fdump-tree-reassoc1-details --param logical-op-non-short-circuit=1" } */
/* { dg-additional-options "-mbranch-cost=2" { target branch_cost } } */

18
gcc/testsuite/gcc.target/nios2/andci.c
View File

@@ -1,18 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2" } */
/* Test generation of Nios II R2 "andci" and "andchi" instructions. */
unsigned int f (unsigned int a)
{
return a & 0xfffffff0;
}
unsigned int g (unsigned int b)
{
return b & 0xfff0ffff;
}
/* { dg-final { scan-assembler "\tandci\t.*" } } */
/* { dg-final { scan-assembler "\tandchi\t.*" } } */

67
gcc/testsuite/gcc.target/nios2/biggot-1.c
View File

@@ -1,67 +0,0 @@
/* Check that the GOT pointer is being initialized correctly to allow
access to the full 64K maximum GOT size for -fpic, rather than only 32K
(which would happen if the GOT pointer points to the base of the GOT,
as the GOT16 and CALL16 relocations are signed). */
/* { dg-options "-fpic" } */
/* { dg-do run { target nios2-*-linux-gnu } } */
extern void abort (void);
static int n = 0;
void
doit (int m)
{
if (m != n)
abort ();
n++;
}
#define X(N) \
void f_##N (void) { doit (0x##N); }
#define F(N) f_##N ();
#define A(N) \
X(N##0) X(N##1) X(N##2) X(N##3) X(N##4) X(N##5) X(N##6) X(N##7) \
X(N##8) X(N##9) X(N##a) X(N##b) X(N##c) X(N##d) X(N##e) X(N##f) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
}
#define B(N) \
A(N##0) A(N##1) A(N##2) A(N##3) A(N##4) A(N##5) A(N##6) A(N##7) \
A(N##8) A(N##9) A(N##a) A(N##b) A(N##c) A(N##d) A(N##e) A(N##f) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
}
#define C(N) \
B(N##0) B(N##1) B(N##2) B(N##3) B(N##4) B(N##5) B(N##6) B(N##7) \
B(N##8) B(N##9) B(N##a) B(N##b) B(N##c) B(N##d) B(N##e) B(N##f) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
}
#define D(N) \
C(N##0) C(N##1) C(N##2) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) \
}
/* This defines 16x16x16x3 leaf functions, requiring something over
48K of GOT space overall. */
D(0)
int
main (void)
{
f_0 ();
if (n != 16*16*16*3)
abort ();
return 0;
}

68
gcc/testsuite/gcc.target/nios2/biggot-2.c
View File

@@ -1,68 +0,0 @@
/* Check that a program that requires large-GOT support builds and
executes without error. This program defines a very large number
of leaf functions; compiled with -fPIC, they all require GOT
entries, which will overflow the range addressible by 16-bit -fpic
offsets by about a factor of 2. */
/* { dg-options "-fPIC" } */
/* { dg-do run { target nios2-*-linux-gnu } } */
extern void abort (void);
static int n = 0;
void
doit (int m)
{
if (m != n)
abort ();
n++;
}
#define X(N) \
void f_##N (void) { doit (0x##N); }
#define F(N) f_##N ();
#define A(N) \
X(N##0) X(N##1) X(N##2) X(N##3) X(N##4) X(N##5) X(N##6) X(N##7) \
X(N##8) X(N##9) X(N##a) X(N##b) X(N##c) X(N##d) X(N##e) X(N##f) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
}
#define B(N) \
A(N##0) A(N##1) A(N##2) A(N##3) A(N##4) A(N##5) A(N##6) A(N##7) \
A(N##8) A(N##9) A(N##a) A(N##b) A(N##c) A(N##d) A(N##e) A(N##f) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
}
#define C(N) \
B(N##0) B(N##1) B(N##2) B(N##3) B(N##4) B(N##5) B(N##6) B(N##7) \
B(N##8) B(N##9) B(N##a) B(N##b) B(N##c) B(N##d) B(N##e) B(N##f) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
}
#define D(N) \
C(N##0) C(N##1) C(N##2) C(N##3) C(N##4) C(N##5) C(N##6) C(N##7) \
void f_##N (void) { \
F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
}
/* This defines 16x16x16x8 leaf functions, requiring something over
128K of GOT space overall. */
D(0)
int
main (void)
{
f_0 ();
if (n != 16*16*16*8)
abort ();
return 0;
}

29
gcc/testsuite/gcc.target/nios2/bmx.c
View File

@@ -1,29 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mbmx" } */
/* Test generation of Nios II R2 BMX instructions. */
struct s {
unsigned int pad1 : 3;
unsigned int bitfield : 20;
unsigned int intfield;
};
void f (struct s *a, struct s *b)
{
a->bitfield = b->bitfield;
}
void g (struct s *a, struct s *b)
{
a->bitfield = b->intfield;
}
void h (struct s *a, struct s *b)
{
a->intfield = b->bitfield;
}
/* { dg-final { scan-assembler "\tmerge\t.*, 22, 3" } } */
/* { dg-final { scan-assembler "\tinsert\t.*, 22, 3" } } */
/* { dg-final { scan-assembler "\textract\t.*, 22, 3" } } */

24
gcc/testsuite/gcc.target/nios2/cdx-add.c
View File

@@ -1,24 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mcdx" } */
/* Check generation of R2 CDX add.n and addi.n instructions. */
int f (int a, int b)
{
return a + b;
}
int g (int a)
{
return a + 32;
}
int h (int a)
{
return a + 33;
}
/* { dg-final { scan-assembler "\tadd\\.n\t.*" } } */
/* { dg-final { scan-assembler "\taddi\\.n\t.*, 32" } } */
/* { dg-final { scan-assembler "\taddi\t.*, 33" } } */

44
gcc/testsuite/gcc.target/nios2/cdx-branch.c
View File

@@ -1,44 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-Os -march=r2 -mcdx" } */
/* Check generation of R2 CDX br.n, beqz.n, bnez.n instructions. */
int f (int a, int b, int c)
{
if (a == 0)
return b;
else
return c;
}
int g (int a, int b, int c)
{
if (a != 0)
return b;
else
return c;
}
extern int i (int);
extern int j (int);
extern int k (int);
int h (int a, int b)
{
int x;
/* As well as the conditional branch for the "if", there has to be
an unconditional branch from one branch of the "if" to
the return statement. We compile this testcase with -Os to
avoid insertion of a duplicate epilogue in place of the branch. */
if (a == b)
x = i (37);
else
x = j (42);
return x + a + k (x);
}
/* { dg-final { scan-assembler "\tbeqz\\.n\t.*" } } */
/* { dg-final { scan-assembler "\tbnez\\.n\t.*" } } */
/* { dg-final { scan-assembler "\tbeq\t|\tbne\t" } } */
/* { dg-final { scan-assembler "\tbr\\.n\t.*" } } */

25
gcc/testsuite/gcc.target/nios2/cdx-callret.c
View File

@@ -1,25 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mcdx" } */
/* Check generation of R2 CDX callr.n, jmpr.n, ret.n instructions. */
typedef int (*F) (void);
int x (F f)
{
f ();
/* Note that the compiler might generate a return via pop.n or ldwm;
the test below is to make sure that it doesn't generate a 32-bit
return instruction. */
return 3;
}
int y (F f)
{
return f ();
}
/* { dg-final { scan-assembler "\tcallr\\.n\t.*" } } */
/* { dg-final { scan-assembler-not "\tret$" } } */
/* { dg-final { scan-assembler "\tjmpr\\.n\t.*" } } */

24
gcc/testsuite/gcc.target/nios2/cdx-ldstwm-1.c
View File

@@ -1,24 +0,0 @@
/* { dg-do assemble } */
/* { dg-options "-O3 -fomit-frame-pointer -funroll-all-loops -finline-functions -march=r2 -mcdx -w -fpermissive" } */
/* Based on gcc.c-torture/compile/920501-23.c.
This test used to result in assembler errors with R2 CDX because of
a bug in regrename; it wasn't re-validating insns after renaming, so
ldwm/stwm instructions with incorrect registers were being emitted. */
typedef unsigned char qi;
typedef unsigned short hi;
typedef unsigned long si;
typedef unsigned long long di;
subi(a){return 100-a;}
add(a,b){return a+b;}
mul(a){return 85*a;}
memshift(p)unsigned*p;{unsigned x;for(;;){x=*p++>>16;if(x)return x;}}
ldw(xp)si*xp;{return xp[4];}
ldws_m(xp)si*xp;{si x;do{x=xp[3];xp+=3;}while(x);}
postinc_si(p)si*p;{si x;for(;;){x=*p++;if(x)return x;}}
preinc_si(p)si*p;{si x;for(;;){x=*++p;if(x)return x;}}
postinc_di(p)di*p;{di x;for(;;){x=*p++;if(x)return x;}}
preinc_di(p)di*p;{di x;for(;;){x=*++p;if(x)return x;}}
inc_overlap(p,a)di*p;{do{p=*(di**)p;p=(di*)((int)p+4);}while(*p);}
di move_di(p,p2)di*p,*p2;{di x=p;p2=((di*)x)[1];return p2[1];}

69
gcc/testsuite/gcc.target/nios2/cdx-ldstwm-2.c
View File

@@ -1,69 +0,0 @@
/* { dg-do assemble } */
/* { dg-options "-O3 -fomit-frame-pointer -funroll-loops -march=r2 -mcdx -w" } */
extern void abort (void);
extern int exit (int);
/* Based on gcc.c-torture/execute/20021120-1.c.
This test used to result in assembler errors with R2 CDX because of
a bug in regrename; it wasn't re-validating insns after renaming, so
ldwm/stwm instructions with incorrect registers were being emitted. */
/* Macros to emit "L Nxx R" for each octal number xx between 000 and 037. */
#define OP1(L, N, R, I, J) L N##I##J R
#define OP2(L, N, R, I) \
OP1(L, N, R, 0, I), OP1(L, N, R, 1, I), \
OP1(L, N, R, 2, I), OP1(L, N, R, 3, I)
#define OP(L, N, R) \
OP2(L, N, R, 0), OP2(L, N, R, 1), OP2(L, N, R, 2), OP2(L, N, R, 3), \
OP2(L, N, R, 4), OP2(L, N, R, 5), OP2(L, N, R, 6), OP2(L, N, R, 7)
/* Declare 32 unique variables with prefix N. */
#define DECLARE(N) OP (, N,)
/* Copy 32 variables with prefix N from the array at ADDR.
Leave ADDR pointing to the end of the array. */
#define COPYIN(N, ADDR) OP (, N, = *(ADDR++))
/* Likewise, but copy the other way. */
#define COPYOUT(N, ADDR) OP (*(ADDR++) =, N,)
/* Add the contents of the array at ADDR to 32 variables with prefix N.
Leave ADDR pointing to the end of the array. */
#define ADD(N, ADDR) OP (, N, += *(ADDR++))
volatile double gd[32];
volatile float gf[32];
void foo (int n)
{
double DECLARE(d);
float DECLARE(f);
volatile double *pd;
volatile float *pf;
int i;
pd = gd; COPYIN (d, pd);
for (i = 0; i < n; i++)
{
pf = gf; COPYIN (f, pf);
pd = gd; ADD (d, pd);
pd = gd; ADD (d, pd);
pd = gd; ADD (d, pd);
pf = gf; COPYOUT (f, pf);
}
pd = gd; COPYOUT (d, pd);
}
int main ()
{
int i;
for (i = 0; i < 32; i++)
gd[i] = i, gf[i] = i;
foo (1);
for (i = 0; i < 32; i++)
if (gd[i] != i * 4 || gf[i] != i)
abort ();
exit (0);
}

61
gcc/testsuite/gcc.target/nios2/cdx-loadstore.c
View File

@@ -1,61 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mcdx" } */
/* Check generation of R2 CDX load/store instructions. */
unsigned char ldb (unsigned char *p)
{
return p[7];
}
unsigned short ldh (unsigned short *p)
{
return p[7];
}
unsigned int ldw (unsigned int *p)
{
return p[7];
}
void stb (unsigned char *p, unsigned char x)
{
p[15] = x;
}
void sth (unsigned short *p, unsigned short x)
{
p[15] = x;
}
void stw (unsigned int *p, unsigned int x)
{
p[15] = x;
}
void no_cdx_stb (unsigned char *p, unsigned char x)
{
p[16] = x;
}
void no_cdx_sth (unsigned short *p, unsigned short x)
{
p[16] = x;
}
void no_cdx_stw (unsigned int *p, unsigned int x)
{
p[16] = x;
}
/* { dg-final { scan-assembler "\tldbu\\.n\t.*, 7\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tldhu\\.n\t.*, 14\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tldw\\.n\t.*, 28\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tstb\\.n\t.*, 15\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tsth\\.n\t.*, 30\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tstw\\.n\t.*, 60\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tstb\t.*, 16\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tsth\t.*, 32\\(.*\\)" } } */
/* { dg-final { scan-assembler "\tstw\t.*, 64\\(.*\\)" } } */

43
gcc/testsuite/gcc.target/nios2/cdx-logical.c
View File

@@ -1,43 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mcdx" } */
/* Check generation of R2 CDX and.n, andi.n, or.n, xor.n, and not.n
instructions.
and.n, or.n, and x.n require one of the input registers to be the same
as the output register. Since the tests below want to put the result
in the return value register, they use this function to make sure that
one of the input operands is also already in the return register. */
extern unsigned int x (unsigned int a);
unsigned int f (unsigned int a, unsigned int b)
{
return x (a) & b;
}
unsigned int g (unsigned int a)
{
return a & 31;
}
unsigned int h (unsigned int a, unsigned int b)
{
return x (a) | b;
}
unsigned int i (unsigned int a, unsigned int b)
{
return x (a) ^ b;
}
unsigned int j (unsigned int a)
{
return ~a;
}
/* { dg-final { scan-assembler "\tand\\.n\t.*" } } */
/* { dg-final { scan-assembler "\tandi\\.n\t.*, 31" } } */
/* { dg-final { scan-assembler "\tor\\.n\t.*" } } */
/* { dg-final { scan-assembler "\txor\\.n\t.*" } } */
/* { dg-final { scan-assembler "\tnot\\.n\t.*" } } */

20
gcc/testsuite/gcc.target/nios2/cdx-mov.c
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@@ -1,20 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mcdx" } */
/* Check generation of R2 CDX mov.n and movi.n instructions. */
extern void f (int a, int b, int c, int d);
int g (int x, int y, int z)
{
f (100, x, y, z);
return -1;
}
/* We should always get mov.n and never mov when compiling with -mcdx. */
/* { dg-final { scan-assembler "\tmov\\.n\t.*" } } */
/* { dg-final { scan-assembler-not "\tmov\t.*" } } */
/* Both of the constant loads are expressible with movi.n. */
/* { dg-final { scan-assembler "\tmovi\\.n\t.*, 100" } } */
/* { dg-final { scan-assembler "\tmovi\\.n\t.*, -1" } } */

32
gcc/testsuite/gcc.target/nios2/cdx-shift.c
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@@ -1,32 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mcdx" } */
/* Check generation of R2 CDX and.n, andi.n, or.n, xor.n, and not.n
instructions. */
extern unsigned int x (unsigned int a);
unsigned int f (unsigned int a, unsigned int b)
{
return x (a) << b;
}
unsigned int g (unsigned int a)
{
return x (a) << 24;
}
unsigned int h (unsigned int a, unsigned int b)
{
return x (a) >> b;
}
unsigned int i (unsigned int a, unsigned int b)
{
return x (a) >> 24;
}
/* { dg-final { scan-assembler "\tsll\\.n\t.*" } } */
/* { dg-final { scan-assembler "\tslli\\.n\t.*, 24" } } */
/* { dg-final { scan-assembler "\tsrl\\.n\t.*" } } */
/* { dg-final { scan-assembler "\tsrli\\.n\t.*, 24" } } */

23
gcc/testsuite/gcc.target/nios2/cdx-sub.c
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@@ -1,23 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mcdx" } */
/* Check generation of R2 CDX sub.n, subi.n, and neg.n instructions. */
int f (int a, int b)
{
return a - b;
}
int g (int a)
{
return a - 32;
}
int h (int a)
{
return -a;
}
/* { dg-final { scan-assembler "\tsub\\.n\t.*" } } */
/* { dg-final { scan-assembler "\tsubi\\.n\t.*, 32" } } */
/* { dg-final { scan-assembler "\tneg\\.n\t.*" } } */

19
gcc/testsuite/gcc.target/nios2/const-addr-1.c
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@@ -1,19 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-times "stw\tr., 12816\\(r\[2-9\]\\)" 1 } } */
/* { dg-final { scan-assembler-times "stw\tr., 12816\\(r0\\)" 1 } } */
/* { dg-final { scan-assembler-times "stw\tr., 528\\(r0\\)" 1 } } */
/* These functions should not spill to stack. */
/* { dg-final { scan-assembler-not "addi\tsp, sp" } } */
/* { dg-final { scan-assembler-not "spdeci" } } */
#define addr1 ((volatile int *) 0x43210)
#define addr2 ((volatile int *) 0x3210)
#define addr3 ((volatile int *) 0x210)
#define SET(l,r) (*(l) = (r))
void foo1 (int x) { SET (addr1, x); }
void foo2 (int x) { SET (addr2, x); }
void foo3 (int x) { SET (addr3, x); }

18
gcc/testsuite/gcc.target/nios2/const-addr-2.c
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@@ -1,18 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-march=r1 -mno-cdx -mno-bmx -O2" } */
/* { dg-final { scan-assembler-times "stwio\tr., 12816\\(r\[2-9\]\\)" 1 } } */
/* { dg-final { scan-assembler-times "stwio\tr., 12816\\(r0\\)" 1 } } */
/* { dg-final { scan-assembler-times "stwio\tr., 528\\(r0\\)" 1 } } */
/* These functions should not spill to stack. */
/* { dg-final { scan-assembler-not "addi\tsp, sp" } } */
#define addr1 ((volatile int *) 0x43210)
#define addr2 ((volatile int *) 0x3210)
#define addr3 ((volatile int *) 0x210)
#define SET(l,r) __builtin_stwio ((l), (r))
void foo1 (int x) { SET (addr1, x); }
void foo2 (int x) { SET (addr2, x); }
void foo3 (int x) { SET (addr3, x); }

20
gcc/testsuite/gcc.target/nios2/const-addr-3.c
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@@ -1,20 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-march=r2 -mno-cdx -mno-bmx -O2" } */
/* { dg-final { scan-assembler-times "stwio\tr., 0\\(r" 2 } } */
/* { dg-final { scan-assembler-times "stwio\tr., 528\\(r0\\)" 1 } } */
/* These functions should not spill to stack. */
/* { dg-final { scan-assembler-not "addi\tsp, sp" } } */
/* On R2, stwio takes only a 12-bit displacement so foo1 and foo2 need
to use register indirect addressing. */
#define addr1 ((volatile int *) 0x43210)
#define addr2 ((volatile int *) 0x3210)
#define addr3 ((volatile int *) 0x210)
#define SET(l,r) __builtin_stwio ((l), (r))
void foo1 (int x) { SET (addr1, x); }
void foo2 (int x) { SET (addr2, x); }
void foo3 (int x) { SET (addr3, x); }

22
gcc/testsuite/gcc.target/nios2/custom-fp-1.c
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@@ -1,22 +0,0 @@
/* Test specification of custom instructions via command-line options. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only -mcustom-fmaxs=246 -mcustom-fmins=247 -mcustom-fsqrts=251" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
void
custom_fp (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
result[2] = sqrtf (operand_a);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
/* { dg-final { scan-assembler "custom\\t251, .* # fsqrts .*" } } */

26
gcc/testsuite/gcc.target/nios2/custom-fp-2.c
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@@ -1,26 +0,0 @@
/* Test specification of custom instructions via pragmas. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
#pragma GCC target ("custom-fmaxs=246")
#pragma GCC target ("custom-fmins=247")
#pragma GCC target ("custom-fsqrts=251")
void
custom_fp (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
result[2] = sqrtf (operand_a);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
/* { dg-final { scan-assembler "custom\\t251, .* # fsqrts .*" } } */

26
gcc/testsuite/gcc.target/nios2/custom-fp-2b.c
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@@ -1,26 +0,0 @@
/* Test specification of custom instructions via pragmas. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only -save-temps" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
#pragma GCC target ("custom-fmaxs=246")
#pragma GCC target ("custom-fmins=247")
#pragma GCC target ("custom-fsqrts=251")
void
custom_fp (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
result[2] = sqrtf (operand_a);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
/* { dg-final { scan-assembler "custom\\t251, .* # fsqrts .*" } } */

26
gcc/testsuite/gcc.target/nios2/custom-fp-3.c
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@@ -1,26 +0,0 @@
/* Test specification of custom instructions via function attributes. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmaxs=246,custom-fmins=247,custom-fsqrts=251")));
void
custom_fp (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
result[2] = sqrtf (operand_a);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
/* { dg-final { scan-assembler "custom\\t251, .* # fsqrts .*" } } */

29
gcc/testsuite/gcc.target/nios2/custom-fp-4.c
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@@ -1,29 +0,0 @@
/* Test conflict between pragma and attribute specification of custom
instructions. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
/* This test case is expected to cause an error because GCC does not know
how to merge different custom instruction attribute sets. The extern
declaration sees the options specified by both the pragma and the function
attribute, but the function definition sees only the pragma options. */
#pragma GCC target ("custom-fmaxs=246")
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmins=247")));
void
custom_fp (float operand_a, float operand_b, float *result)
{ /* { dg-error "conflicting" } */
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}

26
gcc/testsuite/gcc.target/nios2/custom-fp-5.c
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@@ -1,26 +0,0 @@
/* Test that forward declaration and definition don't conflict when used
with pragma specification of custom instructions. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
#pragma GCC target ("custom-fmaxs=246,custom-fmins=247")
extern void
custom_fp (float operand_a, float operand_b, float *result);
void
custom_fp (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */

30
gcc/testsuite/gcc.target/nios2/custom-fp-6.c
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@@ -1,30 +0,0 @@
/* Test conflict between pragma and attribute specification of custom
instructions. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
/* This test case is expected to cause an error because GCC does not know
how to merge different custom instruction attribute sets, even if they
do not overlap. */
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmaxs=246")));
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmins=247"))); /* { dg-error "conflicting" } */
void
custom_fp (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}

33
gcc/testsuite/gcc.target/nios2/custom-fp-7.c
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@@ -1,33 +0,0 @@
/* Test that duplicate declarations with the same custom insn attributes
don't cause an error. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
/* This test case is expected to cause an error because GCC does not know
how to merge different custom instruction attribute sets, even if they
do not overlap. */
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmaxs=246,custom-fmins=247")));
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmaxs=246,custom-fmins=247")));
void
custom_fp (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */

24
gcc/testsuite/gcc.target/nios2/custom-fp-8.c
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@@ -1,24 +0,0 @@
/* Test whitespace skipping in target attributes. */
/* { dg-do compile } */
#pragma GCC target ("custom-fdivs=246")
#pragma GCC target (" custom-fdivs=246")
#pragma GCC target ("custom-fdivs =246")
#pragma GCC target ("custom-fdivs= 246")
#pragma GCC target ("custom-fdivs=246 ")
#pragma GCC target ("custom-fdivs=246,custom-fabss=247")
#pragma GCC target ("custom-fdivs=246 ,custom-fabss=247")
#pragma GCC target ("custom-fdivs=246, custom-fabss=247")
#pragma GCC target ("custom-fdivs=246 , custom-fabss=247")
void foo (void) __attribute__ ((target ("custom-fcmpnes=226,custom-fcmpeqs=227")));
void foo (void) __attribute__ ((target ("custom-fcmpnes =226 ,custom-fcmpeqs=227")));
void foo (void) __attribute__ ((target ("custom-fcmpnes= 226, custom-fcmpeqs=227")));
void foo (void) __attribute__ ((target (" custom-fcmpnes=226 , custom-fcmpeqs = 227")));
void foo (void) __attribute__ ((target (" custom-fcmpnes=226 ,custom-fcmpeqs =227 ")));
#pragma GCC target ("custom-fpu-cfg=60-1")
#pragma GCC target ("custom-fpu-cfg =60-1 ")
#pragma GCC target (" custom-fpu-cfg= 60-1 ")

53
gcc/testsuite/gcc.target/nios2/custom-fp-cmp-1.c
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@@ -1,53 +0,0 @@
/* Test generation of floating-point compare custom instructions. */
/* { dg-do compile } */
/* { dg-options "-O1" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#pragma GCC target ("custom-frdxhi=40")
#pragma GCC target ("custom-frdxlo=41")
#pragma GCC target ("custom-frdy=42")
#pragma GCC target ("custom-fwrx=43")
#pragma GCC target ("custom-fwry=44")
#pragma GCC target ("custom-fcmpeqs=200")
int
test_fcmpeqs (float a, float b)
{
return (a == b);
}
/* { dg-final { scan-assembler "custom\\t200, .* # fcmpeqs .*" } } */
#pragma GCC target ("custom-fcmpgtd=201")
int
test_fcmpgtd (double a, double b)
{
return (a > b);
}
/* { dg-final { scan-assembler "custom\\t201, .* # fcmpgtd .*" } } */
#pragma GCC target ("custom-fcmples=202")
int
test_fcmples (float a, float b)
{
return (a <= b);
}
/* { dg-final { scan-assembler "custom\\t202, .* # fcmples .*" } } */
#pragma GCC target ("custom-fcmpned=203")
int
test_fcmpned (double a, double b)
{
return (a != b);
}
/* { dg-final { scan-assembler "custom\\t203, .* # fcmpned .*" } } */

72
gcc/testsuite/gcc.target/nios2/custom-fp-conversion.c
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@@ -1,72 +0,0 @@
/* Test generation of conversion custom instructions. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only -funsafe-math-optimizations -fno-math-errno" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. Also, -fno-math-errno is required
to inline lroundf. */
#include <stdio.h>
#include <math.h>
#pragma GCC target ("custom-frdxhi=40")
#pragma GCC target ("custom-frdxlo=41")
#pragma GCC target ("custom-frdy=42")
#pragma GCC target ("custom-fwrx=43")
#pragma GCC target ("custom-fwry=44")
#pragma GCC target ("custom-fextsd=100")
#pragma GCC target ("custom-fixdi=101")
#pragma GCC target ("custom-fixdu=102")
#pragma GCC target ("custom-fixsi=103")
#pragma GCC target ("custom-fixsu=104")
#pragma GCC target ("custom-floatid=105")
#pragma GCC target ("custom-floatis=106")
#pragma GCC target ("custom-floatud=107")
#pragma GCC target ("custom-floatus=108")
#pragma GCC target ("custom-ftruncds=109")
#pragma GCC target ("custom-round=110")
typedef struct data {
double fextsd;
int fixdi;
unsigned fixdu;
int fixsi;
unsigned fixsu;
double floatid;
float floatis;
double floatud;
float floatus;
float ftruncds;
int round;
} data_t;
void
custom_fp (int i, unsigned u, float f, double d, data_t *out)
{
out->fextsd = (double) f;
out->fixdi = (int) d;
out->fixdu = (unsigned) d;
out->fixsi = (int) f;
out->fixsu = (unsigned) f;
out->floatid = (double) i;
out->floatis = (float) i;
out->floatud = (double) u;
out->floatus = (float) u;
out->ftruncds = (float) d;
out->round = lroundf (f);
}
/* { dg-final { scan-assembler "custom\\t100, .* # fextsd .*" } } */
/* { dg-final { scan-assembler "custom\\t101, .* # fixdi .*" } } */
/* { dg-final { scan-assembler "custom\\t102, .* # fixdu .*" } } */
/* { dg-final { scan-assembler "custom\\t103, .* # fixsi .*" } } */
/* { dg-final { scan-assembler "custom\\t104, .* # fixsu .*" } } */
/* { dg-final { scan-assembler "custom\\t105, .* # floatid .*" } } */
/* { dg-final { scan-assembler "custom\\t106, .* # floatis .*" } } */
/* { dg-final { scan-assembler "custom\\t107, .* # floatud .*" } } */
/* { dg-final { scan-assembler "custom\\t108, .* # floatus .*" } } */
/* { dg-final { scan-assembler "custom\\t109, .* # ftruncds .*" } } */
/* { dg-final { scan-assembler "custom\\t110, .* # round .*" } } */

86
gcc/testsuite/gcc.target/nios2/custom-fp-double.c
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@@ -1,86 +0,0 @@
/* Test generation of all double-float custom instructions. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only -funsafe-math-optimizations" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
#pragma GCC target ("custom-frdxhi=40")
#pragma GCC target ("custom-frdxlo=41")
#pragma GCC target ("custom-frdy=42")
#pragma GCC target ("custom-fwrx=43")
#pragma GCC target ("custom-fwry=44")
#pragma GCC target ("custom-fabsd=100")
#pragma GCC target ("custom-faddd=101")
#pragma GCC target ("custom-fatand=102")
#pragma GCC target ("custom-fcosd=103")
#pragma GCC target ("custom-fdivd=104")
#pragma GCC target ("custom-fexpd=105")
#pragma GCC target ("custom-flogd=106")
#pragma GCC target ("custom-fmaxd=107")
#pragma GCC target ("custom-fmind=108")
#pragma GCC target ("custom-fmuld=109")
#pragma GCC target ("custom-fnegd=110")
#pragma GCC target ("custom-fsind=111")
#pragma GCC target ("custom-fsqrtd=112")
#pragma GCC target ("custom-fsubd=113")
#pragma GCC target ("custom-ftand=114")
#pragma GCC target ("custom-fcmpeqd=200")
#pragma GCC target ("custom-fcmpged=201")
#pragma GCC target ("custom-fcmpgtd=202")
#pragma GCC target ("custom-fcmpled=203")
#pragma GCC target ("custom-fcmpltd=204")
#pragma GCC target ("custom-fcmpned=205")
void
custom_fp (double a, double b, double *fp, int *ip)
{
fp[0] = fabs (a);
fp[1] = a + b;
fp[2] = atan (a);
fp[3] = cos (a);
fp[4] = a / b;
fp[5] = exp (a);
fp[6] = log (a);
fp[7] = fmax (a, b);
fp[8] = fmin (a, b);
fp[9] = a * b;
fp[10] = -b;
fp[11] = sin (b);
fp[12] = sqrt (a);
fp[13] = a - b;
fp[14] = tan (a);
ip[0] = (a == fp[0]);
ip[1] = (a >= fp[1]);
ip[2] = (a > fp[2]);
ip[3] = (a <= fp[3]);
ip[4] = (a < fp[4]);
ip[5] = (a != fp[5]);
}
/* { dg-final { scan-assembler "custom\\t100, .* # fabsd .*" } } */
/* { dg-final { scan-assembler "custom\\t101, .* # faddd .*" } } */
/* { dg-final { scan-assembler "custom\\t102, .* # fatand .*" } } */
/* { dg-final { scan-assembler "custom\\t103, .* # fcosd .*" } } */
/* { dg-final { scan-assembler "custom\\t104, .* # fdivd .*" } } */
/* { dg-final { scan-assembler "custom\\t105, .* # fexpd .*" } } */
/* { dg-final { scan-assembler "custom\\t106, .* # flogd .*" } } */
/* { dg-final { scan-assembler "custom\\t107, .* # fmaxd .*" } } */
/* { dg-final { scan-assembler "custom\\t108, .* # fmind .*" } } */
/* { dg-final { scan-assembler "custom\\t109, .* # fmuld .*" } } */
/* { dg-final { scan-assembler "custom\\t110, .* # fnegd .*" } } */
/* { dg-final { scan-assembler "custom\\t111, .* # fsind .*" } } */
/* { dg-final { scan-assembler "custom\\t112, .* # fsqrtd .*" } } */
/* { dg-final { scan-assembler "custom\\t113, .* # fsubd .*" } } */
/* { dg-final { scan-assembler "custom\\t114, .* # ftand .*" } } */
/* { dg-final { scan-assembler "custom\\t200, .* # fcmpeqd .*" } } */
/* { dg-final { scan-assembler "custom\\t201, .* # fcmpged .*" } } */
/* { dg-final { scan-assembler "custom\\t202, .* # fcmpgtd .*" } } */
/* { dg-final { scan-assembler "custom\\t203, .* # fcmpled .*" } } */
/* { dg-final { scan-assembler "custom\\t204, .* # fcmpltd .*" } } */
/* { dg-final { scan-assembler "custom\\t205, .* # fcmpned .*" } } */

80
gcc/testsuite/gcc.target/nios2/custom-fp-float.c
View File

@@ -1,80 +0,0 @@
/* Test generation of all single-float custom instructions. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only -funsafe-math-optimizations" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
#pragma GCC target ("custom-fabss=100")
#pragma GCC target ("custom-fadds=101")
#pragma GCC target ("custom-fatans=102")
#pragma GCC target ("custom-fcoss=103")
#pragma GCC target ("custom-fdivs=104")
#pragma GCC target ("custom-fexps=105")
#pragma GCC target ("custom-flogs=106")
#pragma GCC target ("custom-fmaxs=107")
#pragma GCC target ("custom-fmins=108")
#pragma GCC target ("custom-fmuls=109")
#pragma GCC target ("custom-fnegs=110")
#pragma GCC target ("custom-fsins=111")
#pragma GCC target ("custom-fsqrts=112")
#pragma GCC target ("custom-fsubs=113")
#pragma GCC target ("custom-ftans=114")
#pragma GCC target ("custom-fcmpeqs=200")
#pragma GCC target ("custom-fcmpges=201")
#pragma GCC target ("custom-fcmpgts=202")
#pragma GCC target ("custom-fcmples=203")
#pragma GCC target ("custom-fcmplts=204")
#pragma GCC target ("custom-fcmpnes=205")
void
custom_fp (float a, float b, float *fp, int *ip)
{
fp[0] = fabsf (a);
fp[1] = a + b;
fp[2] = atanf (a);
fp[3] = cosf (a);
fp[4] = a / b;
fp[5] = expf (a);
fp[6] = logf (a);
fp[7] = fmaxf (a, b);
fp[8] = fminf (a, b);
fp[9] = a * b;
fp[10] = -b;
fp[11] = sinf (b);
fp[12] = sqrtf (a);
fp[13] = a - b;
fp[14] = tanf (a);
ip[0] = (a == fp[0]);
ip[1] = (a >= fp[1]);
ip[2] = (a > fp[2]);
ip[3] = (a <= fp[3]);
ip[4] = (a < fp[4]);
ip[5] = (a != fp[5]);
}
/* { dg-final { scan-assembler "custom\\t100, .* # fabss .*" } } */
/* { dg-final { scan-assembler "custom\\t101, .* # fadds .*" } } */
/* { dg-final { scan-assembler "custom\\t102, .* # fatans .*" } } */
/* { dg-final { scan-assembler "custom\\t103, .* # fcoss .*" } } */
/* { dg-final { scan-assembler "custom\\t104, .* # fdivs .*" } } */
/* { dg-final { scan-assembler "custom\\t105, .* # fexps .*" } } */
/* { dg-final { scan-assembler "custom\\t106, .* # flogs .*" } } */
/* { dg-final { scan-assembler "custom\\t107, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t108, .* # fmins .*" } } */
/* { dg-final { scan-assembler "custom\\t109, .* # fmuls .*" } } */
/* { dg-final { scan-assembler "custom\\t110, .* # fnegs .*" } } */
/* { dg-final { scan-assembler "custom\\t111, .* # fsins .*" } } */
/* { dg-final { scan-assembler "custom\\t112, .* # fsqrts .*" } } */
/* { dg-final { scan-assembler "custom\\t113, .* # fsubs .*" } } */
/* { dg-final { scan-assembler "custom\\t114, .* # ftans .*" } } */
/* { dg-final { scan-assembler "custom\\t200, .* # fcmpeqs .*" } } */
/* { dg-final { scan-assembler "custom\\t201, .* # fcmpges .*" } } */
/* { dg-final { scan-assembler "custom\\t202, .* # fcmpgts .*" } } */
/* { dg-final { scan-assembler "custom\\t203, .* # fcmples .*" } } */
/* { dg-final { scan-assembler "custom\\t204, .* # fcmplts .*" } } */
/* { dg-final { scan-assembler "custom\\t205, .* # fcmpnes .*" } } */

33
gcc/testsuite/gcc.target/nios2/custom-fp-inline-1.c
View File

@@ -1,33 +0,0 @@
/* Test that you can inline a function with custom insn attributes into
one with the same attributes. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <math.h>
static inline
__attribute__ ((always_inline, target ("custom-fmaxs=246,custom-fmins=247")))
void
custom_fp1 (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmaxs=246,custom-fmins=247")));
void
custom_fp (float operand_a, float operand_b, float *result)
{
custom_fp1 (operand_a, operand_b, result);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */

29
gcc/testsuite/gcc.target/nios2/custom-fp-inline-2.c
View File

@@ -1,29 +0,0 @@
/* Test that you cannot inline a function with custom insn attributes into
one without attributes. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <math.h>
static inline
__attribute__ ((always_inline, target ("custom-fmaxs=246,custom-fmins=247")))
void
custom_fp1 (float operand_a, float operand_b, float *result) /* { dg-error "target specific option mismatch" } */
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}
extern void
custom_fp (float operand_a, float operand_b, float *result);
void
custom_fp (float operand_a, float operand_b, float *result)
{
custom_fp1 (operand_a, operand_b, result);
}

33
gcc/testsuite/gcc.target/nios2/custom-fp-inline-3.c
View File

@@ -1,33 +0,0 @@
/* Test that you can inline a function without custom insn attributes into
one that does have custom insn attributes. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <math.h>
static inline
__attribute__ ((always_inline))
void
custom_fp1 (float operand_a, float operand_b, float *result)
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmaxs=246,custom-fmins=247")));
void
custom_fp (float operand_a, float operand_b, float *result)
{
custom_fp1 (operand_a, operand_b, result);
}
/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */

29
gcc/testsuite/gcc.target/nios2/custom-fp-inline-4.c
View File

@@ -1,29 +0,0 @@
/* Test that you cannot inline a function with custom insn attributes into
one with incompatible attributes. */
/* { dg-do compile } */
/* { dg-options "-O1 -ffinite-math-only" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <math.h>
static inline
__attribute__ ((always_inline, target ("custom-fmaxs=246,custom-fmins=247")))
void
custom_fp1 (float operand_a, float operand_b, float *result) /* { dg-error "target specific option mismatch" } */
{
result[0] = fmaxf (operand_a, operand_b);
result[1] = fminf (operand_a, operand_b);
}
extern void
custom_fp (float operand_a, float operand_b, float *result)
__attribute__ ((target ("custom-fmaxs=200,custom-fmins=201")));
void
custom_fp (float operand_a, float operand_b, float *result)
{
custom_fp1 (operand_a, operand_b, result);
}

28
gcc/testsuite/gcc.target/nios2/custom-fp-lto.c
View File

@@ -1,28 +0,0 @@
/* Test specification of custom instructions via pragma in the presence
of LTO. This test case formerly failed due to PR60179. */
/* { dg-do link } */
/* { dg-require-effective-target lto } */
/* { dg-options "-O1 -flto -flto-partition=one -save-temps" } */
/* -O1 in the options is significant. Without it FP operations may not be
optimized to custom instructions. */
#include <stdio.h>
#include <math.h>
#pragma GCC target ("custom-fabss=224")
float
custom_fp (float operand_a)
{
return fabsf (operand_a);
}
int
main (int argc, char *argv[])
{
return custom_fp ((float)argc) > 1.0;
}
/* { dg-final { scan-lto-assembler "custom\\t224, " } } */

38
gcc/testsuite/gcc.target/nios2/gpopt-all.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O -mgpopt=all" } */
extern int a __attribute__ ((section (".sdata")));
static volatile int b __attribute__ ((section (".sdata"))) = 1;
extern int c __attribute__ ((section (".data")));
static volatile int d __attribute__ ((section (".data"))) = 2;
extern int e;
static volatile int f = 3;
volatile int g __attribute__ ((weak)) = 4;
extern int h[100];
static int i[100];
static int j[100] __attribute__ ((section (".sdata")));
typedef int (*ftype) (int);
extern int foo (int);
extern int bar (int, int*, int*, int*, ftype);
int baz (void)
{
return bar (a + b + c + d + e + f + g, h, i, j, foo);
}
/* { dg-final { scan-assembler "%gprel\\(a\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(b\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(c\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(d\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(e\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(f\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(g\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(h\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(i\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(j\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(foo\\)" } } */

38
gcc/testsuite/gcc.target/nios2/gpopt-data.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O -mgpopt=data" } */
extern int a __attribute__ ((section (".sdata")));
static volatile int b __attribute__ ((section (".sdata"))) = 1;
extern int c __attribute__ ((section (".data")));
static volatile int d __attribute__ ((section (".data"))) = 2;
extern int e;
static volatile int f = 3;
volatile int g __attribute__ ((weak)) = 4;
extern int h[100];
static int i[100];
static int j[100] __attribute__ ((section (".sdata")));
typedef int (*ftype) (int);
extern int foo (int);
extern int bar (int, int*, int*, int*, ftype);
int baz (void)
{
return bar (a + b + c + d + e + f + g, h, i, j, foo);
}
/* { dg-final { scan-assembler "%gprel\\(a\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(b\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(c\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(d\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(e\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(f\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(g\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(h\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(i\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(j\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(foo\\)" } } */

38
gcc/testsuite/gcc.target/nios2/gpopt-global.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O -mgpopt=global" } */
extern int a __attribute__ ((section (".sdata")));
static volatile int b __attribute__ ((section (".sdata"))) = 1;
extern int c __attribute__ ((section (".data")));
static volatile int d __attribute__ ((section (".data"))) = 2;
extern int e;
static volatile int f = 3;
volatile int g __attribute__ ((weak)) = 4;
extern int h[100];
static int i[100];
static int j[100] __attribute__ ((section (".sdata")));
typedef int (*ftype) (int);
extern int foo (int);
extern int bar (int, int*, int*, int*, ftype);
int baz (void)
{
return bar (a + b + c + d + e + f + g, h, i, j, foo);
}
/* { dg-final { scan-assembler "%gprel\\(a\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(b\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(c\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(d\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(e\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(f\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(g\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(h\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(i\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(j\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(foo\\)" } } */

38
gcc/testsuite/gcc.target/nios2/gpopt-gprel-sec.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O -mgpopt=local -mgprel-sec=\\.frog.+" } */
extern int a __attribute__ ((section (".frog1")));
static volatile int b __attribute__ ((section (".frog2"))) = 1;
extern int c __attribute__ ((section (".data")));
static volatile int d __attribute__ ((section (".data"))) = 2;
extern int e;
static volatile int f = 3;
volatile int g __attribute__ ((weak)) = 4;
extern int h[100];
static int i[100];
static int j[100] __attribute__ ((section (".sdata")));
typedef int (*ftype) (int);
extern int foo (int);
extern int bar (int, int*, int*, int*, ftype);
int baz (void)
{
return bar (a + b + c + d + e + f + g, h, i, j, foo);
}
/* { dg-final { scan-assembler "%gprel\\(a\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(b\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(c\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(d\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(e\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(f\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(g\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(h\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(i\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(j\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(foo\\)" } } */

38
gcc/testsuite/gcc.target/nios2/gpopt-local.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O -mgpopt=local" } */
extern int a __attribute__ ((section (".sdata")));
static volatile int b __attribute__ ((section (".sdata"))) = 1;
extern int c __attribute__ ((section (".data")));
static volatile int d __attribute__ ((section (".data"))) = 2;
extern int e;
static volatile int f = 3;
volatile int g __attribute__ ((weak)) = 4;
extern int h[100];
static int i[100];
static int j[100] __attribute__ ((section (".sdata")));
typedef int (*ftype) (int);
extern int foo (int);
extern int bar (int, int*, int*, int*, ftype);
int baz (void)
{
return bar (a + b + c + d + e + f + g, h, i, j, foo);
}
/* { dg-final { scan-assembler "%gprel\\(a\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(b\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(c\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(d\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(e\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(f\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(g\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(h\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(i\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(j\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(foo\\)" } } */

38
gcc/testsuite/gcc.target/nios2/gpopt-none.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O -mgpopt=none" } */
extern int a __attribute__ ((section (".sdata")));
static volatile int b __attribute__ ((section (".sdata"))) = 1;
extern int c __attribute__ ((section (".data")));
static volatile int d __attribute__ ((section (".data"))) = 2;
extern int e;
static volatile int f = 3;
volatile int g __attribute__ ((weak)) = 4;
extern int h[100];
static int i[100];
static int j[100] __attribute__ ((section (".sdata")));
typedef int (*ftype) (int);
extern int foo (int);
extern int bar (int, int*, int*, int*, ftype);
int baz (void)
{
return bar (a + b + c + d + e + f + g, h, i, j, foo);
}
/* { dg-final { scan-assembler-not "%gprel\\(a\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(b\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(c\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(d\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(e\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(f\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(g\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(h\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(i\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(j\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(foo\\)" } } */

38
gcc/testsuite/gcc.target/nios2/gpopt-r0rel-sec.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O -mgpopt=local -mr0rel-sec=\\.frog.+" } */
extern int a __attribute__ ((section (".frog1")));
static volatile int b __attribute__ ((section (".frog2"))) = 1;
extern int c __attribute__ ((section (".data")));
static volatile int d __attribute__ ((section (".data"))) = 2;
extern int e;
static volatile int f = 3;
volatile int g __attribute__ ((weak)) = 4;
extern int h[100];
static int i[100];
static int j[100] __attribute__ ((section (".sdata")));
typedef int (*ftype) (int);
extern int foo (int);
extern int bar (int, int*, int*, int*, ftype);
int baz (void)
{
return bar (a + b + c + d + e + f + g, h, i, j, foo);
}
/* { dg-final { scan-assembler "%lo\\(a\\)\\(r0\\)" } } */
/* { dg-final { scan-assembler "%lo\\(b\\)\\(r0\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(c\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(d\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(e\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(f\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(g\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(h\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(i\\)" } } */
/* { dg-final { scan-assembler "%gprel\\(j\\)" } } */
/* { dg-final { scan-assembler-not "%gprel\\(foo\\)" } } */

20
gcc/testsuite/gcc.target/nios2/gprel-offset.c
View File

@@ -1,20 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
static struct s {
int x;
char y;
} s;
void set (char c)
{
s.y = c;
}
char get (void)
{
return s.y;
}
/* { dg-final { scan-assembler-times "%gprel\\(s\\+4\\)\\(gp\\)" 2 } } */

40
gcc/testsuite/gcc.target/nios2/lo-addr-bypass.c
View File

@@ -1,40 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=r2 -mbypass-cache" } */
/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 12 } } */
/* { dg-final { scan-assembler-not "ldw\t" } } */
/* { dg-final { scan-assembler-not "stw\t" } } */
/* { dg-final { scan-assembler-not "ldwio\tr., %lo" } } */
/* { dg-final { scan-assembler-not "stwio\tr., %lo" } } */
/* Check that we do not generate %lo addresses with R2 ldstio instructions.
%lo requires a 16-bit relocation and on R2 these instructions only have a
12-bit register offset. */
#define TYPE int
struct ss
{
TYPE x1,x2;
};
extern TYPE S1;
extern TYPE S2[];
extern struct ss S3;
extern struct ss S4[];
TYPE *addr1 (void) { return &S1; }
TYPE get1 (void) { return S1; }
void set1 (TYPE value) { S1 = value; }
TYPE *addr2 (int i) { return &(S2[i]); }
TYPE get2 (int i) { return S2[i]; }
void set2 (int i, TYPE value) { S2[i] = value; }
TYPE *addr3 (void) { return &(S3.x2); }
TYPE get3 (void) { return S3.x2; }
void set3 (TYPE value) { S3.x2 = value; }
TYPE *addr4 (int i) { return &(S4[i].x2); }
TYPE get4 (int i) { return S4[i].x2; }
void set4 (int i, TYPE value) { S4[i].x2 = value; }

60
gcc/testsuite/gcc.target/nios2/lo-addr-char.c
View File

@@ -1,60 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */
/* { dg-final { scan-assembler-times "ldbu\tr., %lo" 4 } } */
/* { dg-final { scan-assembler-times "ldb\tr., %lo" 16 } } */
/* { dg-final { scan-assembler-times "stb\tr., %lo" 4 } } */
/* Check that various address forms involving a symbolic constant
with a possible constant offset and/or index register are optimized
to generate a %lo relocation in the load/store instructions instead
of a plain register indirect addressing mode. */
/* Note: get* uses ldhu but ext* uses ldh since TYPE is signed. */
#define TYPE signed char
struct ss
{
TYPE x1,x2;
};
extern TYPE S1;
extern TYPE S2[];
extern struct ss S3;
extern struct ss S4[];
TYPE *addr1 (void) { return &S1; }
TYPE get1 (void) { return S1; }
void set1 (TYPE value) { S1 = value; }
TYPE *addr2 (int i) { return &(S2[i]); }
TYPE get2 (int i) { return S2[i]; }
void set2 (int i, TYPE value) { S2[i] = value; }
TYPE *addr3 (void) { return &(S3.x2); }
TYPE get3 (void) { return S3.x2; }
void set3 (TYPE value) { S3.x2 = value; }
TYPE *addr4 (int i) { return &(S4[i].x2); }
TYPE get4 (int i) { return S4[i].x2; }
void set4 (int i, TYPE value) { S4[i].x2 = value; }
int extw1 (void) { return (int)(S1); }
int extw2 (int i) { return (int)(S2[i]); }
int extw3 (void) { return (int)(S3.x2); }
int extw4 (int i) { return (int)(S4[i].x2); }
unsigned int extwu1 (void) { return (unsigned int)(S1); }
unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); }
unsigned int extwu3 (void) { return (unsigned int)(S3.x2); }
unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); }
short exth1 (void) { return (short)(S1); }
short exth2 (int i) { return (short)(S2[i]); }
short exth3 (void) { return (short)(S3.x2); }
short exth4 (int i) { return (short)(S4[i].x2); }
unsigned short exthu1 (void) { return (unsigned short)(S1); }
unsigned short exthu2 (int i) { return (unsigned short)(S2[i]); }
unsigned short exthu3 (void) { return (unsigned short)(S3.x2); }
unsigned short exthu4 (int i) { return (unsigned short)(S4[i].x2); }

40
gcc/testsuite/gcc.target/nios2/lo-addr-int.c
View File

@@ -1,40 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */
/* { dg-final { scan-assembler-times "ldw\tr., %lo" 4 } } */
/* { dg-final { scan-assembler-times "stw\tr., %lo" 4 } } */
/* Check that various address forms involving a symbolic constant
with a possible constant offset and/or index register are optimized
to generate a %lo relocation in the load/store instructions instead
of a plain register indirect addressing mode. */
#define TYPE int
struct ss
{
TYPE x1,x2;
};
extern TYPE S1;
extern TYPE S2[];
extern struct ss S3;
extern struct ss S4[];
TYPE *addr1 (void) { return &S1; }
TYPE get1 (void) { return S1; }
void set1 (TYPE value) { S1 = value; }
TYPE *addr2 (int i) { return &(S2[i]); }
TYPE get2 (int i) { return S2[i]; }
void set2 (int i, TYPE value) { S2[i] = value; }
TYPE *addr3 (void) { return &(S3.x2); }
TYPE get3 (void) { return S3.x2; }
void set3 (TYPE value) { S3.x2 = value; }
TYPE *addr4 (int i) { return &(S4[i].x2); }
TYPE get4 (int i) { return S4[i].x2; }
void set4 (int i, TYPE value) { S4[i].x2 = value; }

38
gcc/testsuite/gcc.target/nios2/lo-addr-pic.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile { target nios2-*-linux-gnu } } */
/* { dg-options "-O2 -fpic" } */
/* { dg-final { scan-assembler-not "ldw\tr., %lo" } } */
/* { dg-final { scan-assembler-not "stw\tr., %lo" } } */
/* Check that address transformations for symbolic constants do NOT
apply to code compiled with -fPIC, which requires references to
go through the GOT pointer (r22) instead. */
#define TYPE int
struct ss
{
TYPE x1,x2;
};
extern TYPE S1;
extern TYPE S2[];
extern struct ss S3;
extern struct ss S4[];
TYPE *addr1 (void) { return &S1; }
TYPE get1 (void) { return S1; }
void set1 (TYPE value) { S1 = value; }
TYPE *addr2 (int i) { return &(S2[i]); }
TYPE get2 (int i) { return S2[i]; }
void set2 (int i, TYPE value) { S2[i] = value; }
TYPE *addr3 (void) { return &(S3.x2); }
TYPE get3 (void) { return S3.x2; }
void set3 (TYPE value) { S3.x2 = value; }
TYPE *addr4 (int i) { return &(S4[i].x2); }
TYPE get4 (int i) { return S4[i].x2; }
void set4 (int i, TYPE value) { S4[i].x2 = value; }

51
gcc/testsuite/gcc.target/nios2/lo-addr-short.c
View File

@@ -1,51 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */
/* { dg-final { scan-assembler-times "ldhu\tr., %lo" 4 } } */
/* { dg-final { scan-assembler-times "ldh\tr., %lo" 8 } } */
/* { dg-final { scan-assembler-times "sth\tr., %lo" 4 } } */
/* Check that various address forms involving a symbolic constant
with a possible constant offset and/or index register are optimized
to generate a %lo relocation in the load/store instructions instead
of a plain register indirect addressing mode. */
/* Note: get* uses ldhu but ext* uses ldh since TYPE is signed. */
#define TYPE short
struct ss
{
TYPE x1,x2;
};
extern TYPE S1;
extern TYPE S2[];
extern struct ss S3;
extern struct ss S4[];
TYPE *addr1 (void) { return &S1; }
TYPE get1 (void) { return S1; }
void set1 (TYPE value) { S1 = value; }
TYPE *addr2 (int i) { return &(S2[i]); }
TYPE get2 (int i) { return S2[i]; }
void set2 (int i, TYPE value) { S2[i] = value; }
TYPE *addr3 (void) { return &(S3.x2); }
TYPE get3 (void) { return S3.x2; }
void set3 (TYPE value) { S3.x2 = value; }
TYPE *addr4 (int i) { return &(S4[i].x2); }
TYPE get4 (int i) { return S4[i].x2; }
void set4 (int i, TYPE value) { S4[i].x2 = value; }
int extw1 (void) { return (int)(S1); }
int extw2 (int i) { return (int)(S2[i]); }
int extw3 (void) { return (int)(S3.x2); }
int extw4 (int i) { return (int)(S4[i].x2); }
unsigned int extwu1 (void) { return (unsigned int)(S1); }
unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); }
unsigned int extwu3 (void) { return (unsigned int)(S3.x2); }
unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); }

38
gcc/testsuite/gcc.target/nios2/lo-addr-tls.c
View File

@@ -1,38 +0,0 @@
/* { dg-do compile } */
/* { dg-require-effective-target tls } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-not "ldw\tr., %lo" } } */
/* { dg-final { scan-assembler-not "stw\tr., %lo" } } */
/* Check that address transformations for symbolic constants do NOT
apply to TLS variables. */
#define TYPE int
struct ss
{
TYPE x1,x2;
};
extern __thread TYPE S1;
extern __thread TYPE S2[];
extern __thread struct ss S3;
extern __thread struct ss S4[];
TYPE *addr1 (void) { return &S1; }
TYPE get1 (void) { return S1; }
void set1 (TYPE value) { S1 = value; }
TYPE *addr2 (int i) { return &(S2[i]); }
TYPE get2 (int i) { return S2[i]; }
void set2 (int i, TYPE value) { S2[i] = value; }
TYPE *addr3 (void) { return &(S3.x2); }
TYPE get3 (void) { return S3.x2; }
void set3 (TYPE value) { S3.x2 = value; }
TYPE *addr4 (int i) { return &(S4[i].x2); }
TYPE get4 (int i) { return S4[i].x2; }
void set4 (int i, TYPE value) { S4[i].x2 = value; }

58
gcc/testsuite/gcc.target/nios2/lo-addr-uchar.c
View File

@@ -1,58 +0,0 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-times "addi\tr., r., %lo" 4 } } */
/* { dg-final { scan-assembler-times "ldbu\tr., %lo" 20 } } */
/* { dg-final { scan-assembler-times "stb\tr., %lo" 4 } } */
/* Check that various address forms involving a symbolic constant
with a possible constant offset and/or index register are optimized
to generate a %lo relocation in the load/store instructions instead
of a plain register indirect addressing mode. */
#define TYPE unsigned char
struct ss
{
TYPE x1,x2;
};
extern TYPE S1;
extern TYPE S2[];
extern struct ss S3;
extern struct ss S4[];
TYPE *addr1 (void) { return &S1; }
TYPE get1 (void) { return S1; }
void set1 (TYPE value) { S1 = value; }
TYPE *addr2 (int i) { return &(S2[i]); }
TYPE get2 (int i) { return S2[i]; }
void set2 (int i, TYPE value) { S2[i] = value; }
TYPE *addr3 (void) { return &(S3.x2); }
TYPE get3 (void) { return S3.x2; }
void set3 (TYPE value) { S3.x2 = value; }
TYPE *addr4 (int i) { return &(S4[i].x2); }
TYPE get4 (int i) { return S4[i].x2; }
void set4 (int i, TYPE value) { S4[i].x2 = value; }
int extw1 (void) { return (int)(S1); }
int extw2 (int i) { return (int)(S2[i]); }
int extw3 (void) { return (int)(S3.x2); }
int extw4 (int i) { return (int)(S4[i].x2); }
unsigned int extwu1 (void) { return (unsigned int)(S1); }
unsigned int extwu2 (int i) { return (unsigned int)(S2[i]); }
unsigned int extwu3 (void) { return (unsigned int)(S3.x2); }
unsigned int extwu4 (int i) { return (unsigned int)(S4[i].x2); }
short exth1 (void) { return (short)(S1); }
short exth2 (int i) { return (short)(S2[i]); }
short exth3 (void) { return (short)(S3.x2); }
short exth4 (int i) { return (short)(S4[i].x2); }
unsigned short exthu1 (void) { return (unsigned short)(S1); }
unsigned short exthu2 (int i) { return (unsigned short)(S2[i]); }
unsigned short exthu3 (void) { return (unsigned short)(S3.x2); }
unsigned short exthu4 (int i) { return (unsigned short)(S4[i].x2); }

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