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The v7 memory ordering model allows reordering of conditional atomic instructions. To avoid this, make all atomic patterns unconditional. Expand atomic loads and stores for all architectures so the memory access can be wrapped into an UNSPEC. Reviewed-by: Ramana Radhakrishnan <ramana.gcc@googlemail.com> gcc/ChangeLog: PR target/111235 * config/arm/constraints.md: Remove Pf constraint. * config/arm/sync.md (arm_atomic_load<mode>): Add new pattern. (arm_atomic_load_acquire<mode>): Likewise. (arm_atomic_store<mode>): Likewise. (arm_atomic_store_release<mode>): Likewise. (atomic_load<mode>): Switch patterns to define_expand. (atomic_store<mode>): Likewise. (arm_atomic_loaddi2_ldrd): Remove predication. (arm_load_exclusive<mode>): Likewise. (arm_load_acquire_exclusive<mode>): Likewise. (arm_load_exclusivesi): Likewise. (arm_load_acquire_exclusivesi): Likewise. (arm_load_exclusivedi): Likewise. (arm_load_acquire_exclusivedi): Likewise. (arm_store_exclusive<mode>): Likewise. (arm_store_release_exclusivedi): Likewise. (arm_store_release_exclusive<mode>): Likewise. * config/arm/unspecs.md: Add VUNSPEC_LDR and VUNSPEC_STR. gcc/testsuite/ChangeLog: PR target/111235 * gcc.dg/rtl/arm/stl-cond.c: Remove test. * gcc.target/arm/atomic_loaddi_7.c: Fix dmb count. * gcc.target/arm/atomic_loaddi_8.c: Likewise. * gcc.target/arm/pr111235.c: Add new test.
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