Pan Li 8615c855fa [PATCH v1] RISC-V: Fix missed zero extend for unsigned scalar SAT_TRUNC [PR122692]
When the input of the scalar unsigned SAT_TRUNC is not Xmode,
the rtx need to zero extend to Xmode before the underlying
code gen.  Most of other SAT_* code gen has leveraged
the API riscv_extend_to_xmode_reg but still have the ustrunc
missed.  Then results in the failures mentioned in PR.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

	PR target/122692

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_ustrunc): Leverage
	riscv_extend_to_xmode_reg to take care of src rtx.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/pr122692-run-1.C: New test.
	* g++.target/riscv/pr122692-run-2.C: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
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