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In the PR code we have the somewhat rare case that we need to reload a vector subreg of a scalar register, (subreg:V2HI (reg:DI)). What complicates things is that the test is compiled with -mrvv-vector-bits=zvl, so VLS-only mode. Unfortunately, we can still get VLA-named modes that are actually VLS modes (i.e. that have a constant number of units). For moving real VLS modes we simply use (define_insn_and_split "*mov<mode>" [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr") (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] Here, lra recognizes cycle danger, quickly switches to the memory alternative and the resulting code is as expected - we perform a vector load from that memory the DImode reg was spilled to. For VLA (named) modes the mov insn is (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra" [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr") (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr")) (clobber (match_scratch:P 2 "=&r,&r,X"))] The extra clobber here is an optimization: For modes smaller than a full register we want to store the actual size, rather than always the full vector size. If that mode size happens to exceed 32, instead of using an immediate we need to move it to a register so vsetvl can consume it. As the second mov insn above has three operands lra never checks for cycle danger and promptly creates a cycle :) This patch loosens the conditions on the cycle check by allowing a third operand that is a clobber. PR rtl-optimization/123381 gcc/ChangeLog: * lra-constraints.cc (process_alt_operands): Detect cycles in three-operand moves with clobber. (curr_insn_transform): Don't write back a scratch operand. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr123381.c: New test.
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