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This patch introduces the pipeline description for the Synopsys RHX-100 series processor to the RISC-V GCC backend. The RHX-100 features a 10-stage, dual-issue, in-order execution pipeline architecture. It has support for instruction fusion, which will be addressed by subsequent patches. Due to fusion, up to four instructions can be issued in a single cycle. It is modeled as four separate pipelines and the issue_rate is set to four. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Add arc-v-rhx-100-series. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add arcv_rhx100. * config/riscv/riscv.cc (arcv_rhx100_tune_info): New riscv_tune_param. * config/riscv/riscv.md: Add arcv_rhx100 to tune attribute. * doc/riscv-mtune.texi: Add RHX-100 documentation. * config/riscv/arcv-rhx100.md: New file. Co-authored-by: Artemiy Volkov <artemiyv@acm.org> Co-authored-by: Luis Silva <luiss@synopsys.com> Signed-off-by: Michiel Derhaeg <michiel@synopsys.com>
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