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Krister reported that we violate the psABI when one vector argument halfway fits into a register: "Aggregates whose total size is no more than 2×XLEN bits are passed in a pair of registers; if only one register is available, the first XLEN bits are passed in a register and the remaining bits are passed on the stack. If no registers are available, the aggregate is passed on the stack." This patch fixes this oversight and adds a few tests. Regtested on rv64gcv_zvl512b. PR target/123824 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_vls_mode_fits_in_gprs_p): New helper. (riscv_pass_vls_aggregate_in_gpr): Use helper and distribute half-fitting vector to GPR and stack. (riscv_pass_aggregate_in_vr): Reformat comment. (riscv_get_arg_info): Use helper. (riscv_pass_by_reference): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/abi/vls-gpr-1.c: New test. * gcc.target/riscv/abi/vls-gpr-10.c: New test. * gcc.target/riscv/abi/vls-gpr-11.c: New test. * gcc.target/riscv/abi/vls-gpr-12.c: New test. * gcc.target/riscv/abi/vls-gpr-13.c: New test. * gcc.target/riscv/abi/vls-gpr-14.c: New test. * gcc.target/riscv/abi/vls-gpr-2.c: New test. * gcc.target/riscv/abi/vls-gpr-3.c: New test. * gcc.target/riscv/abi/vls-gpr-4.c: New test. * gcc.target/riscv/abi/vls-gpr-5.c: New test. * gcc.target/riscv/abi/vls-gpr-6.c: New test. * gcc.target/riscv/abi/vls-gpr-7.c: New test. * gcc.target/riscv/abi/vls-gpr-8.c: New test. * gcc.target/riscv/abi/vls-gpr-9.c: New test.
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