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The mask-mode vec_init and vec_extract expanders assume that we can create QImode vectors with the same number of units as the mask mode has. XTheadVector does not have fractional-LMUL modes and we ICE when trying to expand the actual insns. An obvioius solution would be to simply disable the autovec expanders for TARGET_XTHEADVECTOR but exactly these optab/mode combination has no fallback in the common expansion code. That's a known problem and should be fixed separately in extract_bit_field_1. For now, though, we do not need to use small modes and can go with full vectors instead. The excess elements don't matter. To that end, this patch uses paradoxical subregs on the source (for vec_extract) and on the destination (for vec_init), leaving the remaining elements undefined. In order to obtain the right "full vector" I needed to adjust get_m1_mode slightly. By default it returns a VLA mode so when introducing a subreg like above we can have (subreg:full_vector_mode (reg:small_vls_vector_mode) 0) where full_vector_mode is a VLA mode and small_vls_vector_mode is a VLS mode. This won't be a valid subreg so the patch adds a VLS_P argument to get_m1_mode that returns a full VLS vector mode. Regtested on rv64gcv_zvl512b. As I didn't have theadvector hardware available I made the new code paths unconditional (so they are active for regular RVV) and re-tested. PR target/124147 gcc/ChangeLog: * config/riscv/autovec.md: Work around fractional-LMUL modes for TARGET_XTHEADVECTOR. * config/riscv/riscv-protos.h (get_m1_mode): Export. * config/riscv/riscv-v.cc (get_m1_mode): Allow to get a VLS m1 vector. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/pr124147.c: New test.
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