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fff26a966b
Consider this code:
int f(int a, int b, int c)
{
return (a ^ b) ^ (a | c);
}
For RISC-V we generate something like this:
xor a1,a0,a1
or a0,a0,a2
xor a0,a1,a0
But this would be better:
andn a0,a2,a0
xor a0,a0,a1
It looks like Roger tackled this earlier with splitters for x86. I'd have
leaned more towards simplify-rtx, but there may be secondary concerns at play.
So I'll attack in the RISC-V target files in a similar manner.
The patch, but not the testcase, have been in my tester for a while, so it's
been bootstrapped and regression tested on the Pioneer and BPI-F3 board and
regression tested on riscv32-elf and riscv64-elf. Obviously I'll wait for
pre-commit CI before moving forward.
PR rtl-optimization/96692
gcc/
* config/riscv/bitmanip.md (xor+xor+ior splitters): New splitters
that ultimately generate andn+xor when possible.
gcc/testsuite
* gcc.target/riscv/pr96692.c: New test.
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