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i386: Fix up last -masm=intel operand of vcvthf82ph [PR124349]

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gas expects for this instruction
vcvthf82ph      xmm30, QWORD PTR [r9]
vcvthf82ph      ymm30, XMMWORD PTR [r9]
vcvthf82ph      zmm30, YMMWORD PTR [r9]
i.e. the memory size is half of the dest register size.
We currently emit it for the last 2 forms but emit XMMWORD PTR
for the first one too.  So, we need %q1 for V8HF and for V16HF/V32HF
can either use just %1 or %x1/%t1.  There is no define_mode_attr
that would provide those, so I've added one just for this insn.

2026-03-05  Jakub Jelinek  <jakub@redhat.com>

	PR target/124349
	* config/i386/sse.md (iptrssebvec_2): New define_mode_attr.
	(cvthf82ph<mode><mask_name>): Use it for -masm=intel input
	operand.

	* gcc.target/i386/avx10_2-pr124349-2.c: New test.
This commit is contained in:
Jakub Jelinek
2026-03-05 10:05:44 +01:00
committed by Jakub Jelinek
parent d828a370db
commit ed29af4100
2 changed files with 45 additions and 1 deletions
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5
gcc/config/i386/sse.md
View File

@@ -32450,6 +32450,9 @@
(define_mode_attr ssebvecmode_2
[(V8HF "V16QI") (V16HF "V16QI") (V32HF "V32QI")])
(define_mode_attr iptrssebvec_2
[(V8HF "q") (V16HF "") (V32HF "")])
(define_int_iterator UNSPEC_VCVTBIASPH2FP8_PACK
[UNSPEC_VCVTBIASPH2BF8 UNSPEC_VCVTBIASPH2BF8S
UNSPEC_VCVTBIASPH2HF8 UNSPEC_VCVTBIASPH2HF8S])
@@ -32626,7 +32629,7 @@
[(match_operand:<ssebvecmode_2> 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTHF82PH))]
"TARGET_AVX10_2"
"vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
"vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptrssebvec_2>1}"
[(set_attr "prefix" "evex")])
(define_int_iterator VPDPWPROD

41
gcc/testsuite/gcc.target/i386/avx10_2-pr124349-2.c Normal file
View File

@@ -0,0 +1,41 @@
/* PR target/124349 */
/* { dg-do assemble { target { avx10_2 && masm_intel } } } */
/* { dg-options "-O2 -mavx10.2 -masm=intel" } */
#include <x86intrin.h>
__m128h
foo (__m128i *p)
{
return _mm_cvthf8_ph (*p);
}
__m128h
bar (__m128i *p, __m128h w, __mmask8 u)
{
return _mm_mask_cvthf8_ph (w, u, *p);
}
__m256h
baz (__m128i *p)
{
return _mm256_cvthf8_ph (*p);
}
__m256h
qux (__m128i *p, __m256h w, __mmask16 u)
{
return _mm256_mask_cvthf8_ph (w, u, *p);
}
__m512h
fred (__m256i *p)
{
return _mm512_cvthf8_ph (*p);
}
__m512h
corge (__m256i *p, __m512h w, __mmask32 u)
{
return _mm512_mask_cvthf8_ph (w, u, *p);
}