The following builds with -std=c++11 and c++14 and c++17 and c++20 and c++23
and c++26.
I see the u8 string literals are mixed e.g. with strerror, so in
-fexec-charset=IBM1047 there will still be garbage, so am not 100% sure if
the u8 literals everywhere are worth it either.
2025-11-21 Jakub Jelinek <jakub@redhat.com>
* cody.hh (S2C): For __cpp_char8_t >= 201811 use char8_t instead of
char in argument type.
(MessageBuffer::Space): Revert 2025-11-15 change.
(MessageBuffer::Append): For __cpp_char8_t >= 201811 add overload
with char8_t const * type of first argument.
(Packet::Packet): Similarly for first argument.
* client.cc (CommunicationError, Client::ProcessResponse,
Client::Connect, ConnectResponse, PathnameResponse, OKResponse,
IncludeTranslateResponse): Cast u8 string literals to (const char *)
where needed.
* server.cc (Server::ProcessRequests, ConnectRequest): Likewise.
The following removes the confusion around num_mask_args that was
added to properly "guess" the number of mask elements in a AVX512
mask that's just represented as int. The actual mistake lies in
the mixup of 'ncopies' which is used to track the number of
OMP SIMD calls to be emitted rather than the number of input
vectors. So this reverts the earlier r16-5374-g5c2fdfc24e343c,
uses the proper 'ncopies' for loop mask record/query and adjusts
the guessing of the SIMD arg mask elements.
PR tree-optimization/122762
PR tree-optimization/122736
PR tree-optimization/122790
* cgraph.h (cgraph_simd_clone_arg::linear_step): Document
use for SIMD_CLONE_ARG_TYPE_MASK.
* omp-simd-clone.cc (simd_clone_adjust_argument_types):
Record the number of mask arguments in linear_step if
mask_mode is not VOIDmode.
* tree-vect-stmts.cc (vectorizable_simd_clone_call):
Remove num_mask_args computation, use a proper ncopies
to query/register loop masks, use linear_step for the
number of mask arguments when determining the number of
mask elements in a mask argument.
* gcc.dg/vect/vect-simd-clone-23.c: New testcase.
For AVX512 style masking we fail to apply loop masking to a conditional
OMP SIMD call.
PR tree-optimization/122778
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Honor
a loop mask when passing the conditional mask with AVX512
style masking.
* gcc.dg/vect/vect-simd-clone-22.c: New testcase.
* gcc.dg/vect/vect-simd-clone-22a.c: Likewise.
This PR reports that our __reference_*_from_temporary ignore access
control. The reason is that we only check if implicit_conversion
works, but not if the conversion can actually be performed, via
convert_like.
PR c++/120529
gcc/cp/ChangeLog:
* call.cc (ref_conv_binds_to_temporary): Don't ignore access control.
gcc/testsuite/ChangeLog:
* g++.dg/ext/reference_xes_from_temporary1.C: New test.
Reviewed-by: Jason Merrill <jason@redhat.com>
The following testcase ICEs, because the constexpr ctor in C++14
or later doesn't contain any member initializers and so the
massage_constexpr_body -> build_constexpr_constructor_member_initializers
-> build_data_member_initialization member initialization discovery
looks at the ctor body instead. And while it has various
cases where it punts, including COMPONENT_REF with a VAR_DECL as first
operand on lhs of INIT_EXPR, here there is COMPONENT_REF with
several COMPONENT_REFs and VAR_DECL only inside the innermost.
The following patch makes sure we punt on those as well, instead of
blindly assuming it is anonymous union member initializer or asserting
it is a vtable store.
An alternative to this would be some flag on the INIT_EXPRs created
by perform_member_init and let build_data_member_initialization inspect
only INIT_EXPRs with that flag set.
2025-11-21 Jakub Jelinek <jakub@redhat.com>
PR c++/121445
* constexpr.cc (build_data_member_initialization): Just return
false if member is COMPONENT_REF of COMPONENT_REF with
VAR_P get_base_address.
* g++.dg/cpp1y/constexpr-121445.C: New test.
The x87 control word should be passed as an `unsigned short`. Previous
code passed `unsigned int`, and when building with `-masm=intel`,
__asm__ __volatile__ ("fnstcw\t%0" : "=m" (_cw));
could expand to `fnstcw DWORD PTR [esp+48]` and cause errors like
{standard input}: Assembler messages:
{standard input}:7137: Error: operand size mismatch for `fnstcw'
libgcc/ChangeLog:
PR target/122275
* config/i386/32/dfp-machine.h (DFP_GET_ROUNDMODE): Change `_frnd_orig` to
`unsigned short` for x87 control word.
(DFP_SET_ROUNDMODE): Manipulate the x87 control word as `unsigned short`,
and manipulate the MXCSR as `unsigned int`.
Signed-off-by: LIU Hao <lh_mouse@126.com>
As mentioned in the PR, the COND_SH{L,R} internal fns are expanded without
fallback, their expansion must succeed, and furthermore they don't
differentiate between scalar and vector shift counts, so again both have
to be supported. That is the case of the {ashl,lshr,ashr}v*[hsd]i
patterns which use nonimmediate_or_const_vec_dup_operand predicate for
the shift count, so if the argument isn't const vec dup, it can be always
legitimized by loading into a vector register.
This is not the case of the QImode element conditional vector shifts,
there is no fallback for those and we emit individual element shifts
in that case when not conditional and shift count is not a constant.
So, I'm afraid we can't announce such an expander because then the
vectorizer etc. count with it being fully available.
As I've tried to show in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122598#c9
even without this pattern we can sometimes emit
vgf2p8affineqb $0, .LC0(%rip), %ymm0, %ymm0{%k1}
etc. instructions.
2025-11-21 Jakub Jelinek <jakub@redhat.com>
PR target/122598
* config/i386/predicates.md (const_vec_dup_operand): Remove.
* config/i386/sse.md (cond<<insn><mode> with VI1_AVX512VL iterator):
Remove.
* gcc.target/i386/pr122598.c: New test.
In the testcases, the kernels scheduled on queues 11, 12, 13, 14 have
data dependencies on, respectively, 'b', 'c', 'd', and 'e', as they
write to them.
However, they also have a data dependency on 'a' and 'N', as they read
those.
Previously, the testcases exited 'a' on queue 10 and 'N' on queue 15,
meaning that it was possible for the aforementioned kernels to execute
and to have 'a' and 'N' pulled under their feet.
This patch adds waits for each of the kernels onto queue 10 before
freeing 'a', guaranteeing that 'a' outlives the kernels, and the same on
'N'.
libgomp/ChangeLog:
* testsuite/libgomp.oacc-c-c++-common/data-2-lib.c (explanatory
header): Fix typo.
(main): Insert waits on kernels reading 'a' into queue 10 before
exiting 'a', and waits on kernels reading 'N' into queue 15
before exiting 'N'.
* testsuite/libgomp.oacc-c-c++-common/data-2.c: Ditto.
In r16-4212 I had to tweak two spots in the gimplifier to ignore
gotos jumping to labels with the new VACUOUS_INIT_LABEL_P flag
(set by C++ FE when implementing goto/case interceptors with
extra .DEFERRED_INIT calls, so that jumps over vacuous initialization
are handled properly with the C++26 erroneous behavior requirements).
Except as the following testcase shows, the checks blindly assumed
that gimple_goto_dest operand is a LABEL_DECL, which is not the case
for computed jumps.
The following patch checks that gimple_goto_dest argument is a LABEL_DECL
before testing VACUOUS_INIT_LABEL_P flag on it.
2025-11-21 Jakub Jelinek <jakub@redhat.com>
PR middle-end/122773
* gimplify.cc (collect_fallthrough_labels): Check whether
gimple_goto_dest is a LABEL_DECL before testing VACUOUS_INIT_LABEL_P.
(expand_FALLTHROUGH_r): Likewise.
* gcc.dg/pr122773.c: New test.
Address PR target/120375
Devices without a barrel shifter end up using a sequence of
instructions. These can use the condition codes and/or loop count
register, so those need to be marked as 'clobbered'. These clobbers were
previously added only after split1, which is too late. This patch adds
these clobbers from the beginning, in the define_expand.
Previously, define_insn_and_split *<insn>si3_nobs would match any shift or
rotate instruction and would generate the necessary patterns to emulate a
barrel shifter, but it did not have any output assembly for itself.
In many cases this would create a loop with parallel clobbers. This pattern
is then matched by the <insn>si3_loop pattern.
In the no-barrel-shifter.c test tree code:
;; no-barrel-shifter.c:9: int sign = (x >> 31) & 1;
_2 = x.0_1 >> 31;
in the expand pass becomes the following pattern that matches *lshrsi3_nobs:
(insn 18 17 19 4 (set (reg:SI 153 [ _2 ])
(lshiftrt:SI (reg/v:SI 156 [ x ])
(const_int 31 [0x1f]))) "test2.c":9:24 -1
(nil))
This pattern misses the necessary clobbers and remains untouched until the
split1 pass. Together with the later branch it becomes
;; no-barrel-shifter.c:9: int sign = (x >> 31) & 1;
add.f 0,r0,r0
;; no-barrel-shifter.c:14: if (mag == 0x7f800000)
beq.d .L8
;; no-barrel-shifter.c:9: int sign = (x >> 31) & 1;
rlc r0,0
Leading to an issue: the add.f instructions overwrites CC but beq expects
CC to contain an earlier value indicating mag == 0x7f800000.
Now, these are combined in define_insn_and_split <insn>si3_loop that is
explicitly emitted in the define_expand and already contains the clobbers.
This can then be split into another pattern or remain the loop pattern.
In the expand pass, the same example now becomes:
(insn 18 17 19 4 (parallel [
(set (reg:SI 153 [ _2 ])
(lshiftrt:SI (reg/v:SI 156 [ x ])
(const_int 31 [0x1f])))
(clobber (reg:SI 60 lp_count))
(clobber (reg:CC 61 cc))
]) "test2.c":9:24 -1
(nil))
Because the correct clobbers are now taken into account, the branch condition
is reevaluated by using breq instead of br.
;; no-barrel-shifter.c:9: int sign = (x >> 31) & 1;
add.f 0,r0,r0
rlc r0,0
;; no-barrel-shifter.c:14: if (mag == 0x7f800000)
breq r2,2139095040,.L8
Regtested for arc.
PR target/120375
gcc/ChangeLog:
* config/arc/arc.md (*<insn>si3_nobs): merged with <insn>si3_loop.
(<insn>si3_loop): splits to relevant pattern or emits loop assembly.
(<insn>si3_cnt1_clobber): Removes clobber for shift or rotate by
const1.
gcc/testsuite/ChangeLog:
* gcc.target/arc/no-barrel-shifter.c: New test.
Co-authored-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Loeka Rogge <loeka@synopsys.com>
A previous fix titled "Avoid incorrect errors for duplicate formal
iterator names" caused regressions. This patch cleans it up.
In particular, the previous patch involved calling Preanalyze on
a block statement in order to get the scope created, and then
later calling Analyze on the same block statement. This caused
certain temps created inside the block statement to be
incorrectly duplicated. The fix here is to avoid setting
the Statements of the block until after it has been
preanalyzed.
gcc/ada/ChangeLog:
* exp_ch5.adb (Expand_Formal_Container_Loop):
Preanalyze block with empty statements; then set
the statements later before doing Analyze of the
block.
There is a preceding call to Establish_Transient_Scope in the procedure for
the cases where it is required, and we no longer build the aggregate on the
stack before copying it to the heap for an allocator.
gcc/ada/ChangeLog:
* exp_aggr.adb (Expand_Array_Aggregate): Remove obsolete call to
Establish_Transient_Scope for an allocator in a loop.
* exp_ch7.adb (Establish_Transient_Scope): Adjust description.
Cross-references are used by GNATprove for code that is not in SPARK. They are
sorted using an auxiliary array. This array should be allocated on the heap and
not on stack, because it can be arbitrarily large, especially for
auto-generated code.
gcc/ada/ChangeLog:
* lib-xref.adb (Output_References): Put local array object on the heap.
Is_Redundant_Error_Message is used to filter diagnostic messages
that would appear on the same line to avoid the noise comming from
cascading error messages. However we still want to trigger an error
even if the line already had a warning or a non-serious error at the
same location so that we now that a fatal error has occured and the
compiler knows how to exit correctly in that scenario.
gcc/ada/ChangeLog:
* erroutc.adb (Is_Redundant_Error_Message): Avoid non-serious errors
masking fatal errors.
This updates the description of the various kinds of extra formals after the
latest change made to the implementation.
gcc/ada/ChangeLog:
* exp_ch6.ads (BIP_Formal_Kind): Update description of some values.
gcc/ada/ChangeLog:
* exp_ch4.adb (Expand_N_Op_Eq): Use No instead of not Present.
(Optimize_Length_Comparison): Initialize Is_Zero and Comp variables.
(Safe_In_Place_Array_Op): Do not use local variable to pass data to
nested function Is_Safe_Operand.
Extra formals must not be added to anonymous access to subprogram
types defined in the profile of imported C subprograms.
gcc/ada/ChangeLog:
* sem_ch6.adb (Create_Extra_Formals): Do not add extra formals to
anonymous access to subprogram types defined in the profile of
subprograms that have foreign convention.
A change made a long time ago has introduced a leak of the secondary stack
at run time for unconstrained limited non-controlled arrays in anonymous
contexts, because of the lack of a transient scope in these contexts.
The large comment preceding the call to Establish_Transient_Scope in the
Resolve_Call procedure explains the strategy for build-in-place functions,
so the best course of action is probably to revert the commit and to fix
the original problem along the lines of the comment.
gcc/ada/ChangeLog:
* exp_ch3.adb (Expand_N_Object_Declaration): Delete ancient comment.
* exp_ch6.adb (Expand_Call_Helper): Do not establish a transient
scope for build-in-place functions in anonymous contexts here...
(Make_Build_In_Place_Call_In_Anonymous_Context): ...but here instead.
* sem_attr.adb (Resolve_Attribute) <Attribute_Range>: Remove obsolete
code dealing with transient scopes.
* sem_res.adb (Resolve_Actuals): Likewise.
(Resolve_Call): Adjust comment on the strategy for transient scopes.
This patch fixes the following bug: If a type has an Iterable aspect
(as in the formal containers), and two or more cursor loops of the
form "for C in ..." occur in the same scope, and the cursor type has
discriminants without defaults, the compiler complains incorrectly
about duplicate names "Tc".
This is because the generated declaration of the C object was being
analyzed in the wrong scope. In the discriminated case, an internal
subtype name TcS is generated for each C. Errout "helpfully" removes "S"
in the error message, resulting in a complaint about "Tc". The fix is
to push the correct scope (that of the generated surrounding block
statement) when analyzing the declaration of C.
gcc/ada/ChangeLog:
* exp_ch5.adb (Expand_Formal_Container_Loop):
Analyze Init_Decl in the correct scope. Remove patch-up
code that was needed because we were using the wrong scope.
* exp_ch7.adb (Process_Object_Declaration):
Remove code to unique-ify the name of Master_Node_Id;
no longer needed because of change to exp_ch5.adb.
* sem_warn.adb (Check_References):
Suppress warnings during preanalysis, because we don't
have complete information yet; otherwise, the new Preanalyze
call in exp_ch5.adb generates bogus warnings.
In (any instance of) Ada.Containers.Bounded_Vectors, for the procedure
overload of Append that takes parameters of types Vector and Element_Type,
improve performance in the case where either of the GNAT-defined checks
Container_Checks or Tampering_Check are suppressed.
gcc/ada/ChangeLog:
* libgnat/a-cobove.adb
(Append): Add an equivalent fast path for the case where tampering
checks are suppressed.
Some messages triggered by this switch did not have the
gnatwx tag and were not treated as a continuation of the same
error message.
gcc/ada/ChangeLog:
* freeze.adb (Freeze_Profile): Improve -gnatwx message.
Generic formal type parameters may have an unspecified layout when they are
processed for the -gnatR output, so it's better to skip them entirely.
The change also reverts an earlier change that would output "??" for an
unknown alignment on a type, which is inconsistent and undocumented.
gcc/ada/ChangeLog:
* repinfo.adb (List_Location): Do not output the final comma.
(List_Common_Type_Info): Adjust to above change. Do not output
"??" for an unknown alignment.
(List_Entities): Do not output generic types.
(List_Object_Info): Adjust to above change.
(List_Subprogram_Info): Likewise.
gcc/ada/ChangeLog:
* sem_ch4.adb (Analyze_Call): ensure we generate a reference to the
non limited view of the return type to avoid scenarios where
the with-ed unit is not considered referenced.
Due to the if statement in ipa_compute_jump_functions_for_bb, callback
edges were never constructed for builtin functions unless LTO was
enabled. This patch corrects this behavior, allowing GCC to optimize
callbacks more broadly. It also extends our testing capabilities.
gcc/ChangeLog:
* attr-callback.cc (callback_edge_callee_has_attr): New
function.
* attr-callback.h (callback_edge_callee_has_attr): New function
decl.
* ipa-prop.cc (ipa_compute_jump_functions_for_bb): Don't skip
callback carriers when calculating jump functions.
libgomp/ChangeLog:
* testsuite/libgomp.c/ipcp-cb-spec1.c: Remove LTO requirement.
* testsuite/libgomp.c/ipcp-cb-spec2.c: Likewise.
* testsuite/libgomp.c/ipcp-cb1.c: Likewise.
Signed-off-by: Josef Melcr <josef.melcr@suse.com>
This function is used to determine whether a callback edge should be
kept or not. It was supposed to capture the idea that a callback edge
has been redirected at some point, however, it only considered
redirecting to some clone. However, an edge may not always be
redirected to a clone. For example, common function bodies produced by
icf are not clones. This version of this function should cover all
cases, at least for the time being.
gcc/ChangeLog:
PR ipa/122768
* attr-callback.cc (callback_edge_useful_p): Rewrite the
heuristic, now consider clones as well as icf bodies.
Signed-off-by: Josef Melcr <josef.melcr@suse.com>
When the most significant bit of the 13 bit immediate value in LoongArch
{x}vldi isntruction is set 1, it can generate different numbers based on
the algorithm. This patch adds to support these numbers to be
generated by {x}vldi instruction.
gcc/ChangeLog:
* config/loongarch/constraints.md: Update constraint YI to support
more numbers.
* config/loongarch/loongarch-protos.h
(loongarch_const_vector_vrepli): Rename.
(loongarch_const_vector_vldi): Ditto.
* config/loongarch/loongarch.cc (VLDI_NEG_MASK): New macro.
(loongarch_parse_vldi_const): New function to check if numbers can
be generated by {x}vldi instruction.
(loongarch_const_vector_vrepli): Rename.
(loongarch_const_vector_vldi): Use above function.
(loongarch_const_insns): Call renamed function.
(loongarch_split_vector_move_p): Ditto.
(loongarch_output_move): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-builtin.c: Replace xvrepli
with xvldi.
* gcc.target/loongarch/vector/lasx/lasx-vec-init-2.c: Fix test.
* gcc.target/loongarch/vector/lsx/lsx-builtin.c: Repalce vrepli with
vldi.
* gcc.target/loongarch/vrepli.c: Ditto.
* gcc.target/loongarch/vector/lasx/lasx-xvldi-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vldi-2.c: New test.
UNSPEC_LSX_VREPLVEI_MIRROR describes the mirroring operation that copies
the lower 64 bits of a 128-bit register to the upper 64 bits. So in any
mode, the value range of op2 can only be 0 or 1 for the vreplvei.d insn.
gcc/ChangeLog:
* config/loongarch/lsx.md: Fix predicate.
Only do iterative analysis if it might be worthwhile.
PR tree-optimization/121345
gcc/
* gimple-range-phi.cc (phi_group::calculate_using_modifier): Restore
performance loss by being more selective when iterating.
When using directly __gnu_debug::vector the std::erase_if is called with a
reference to the std::vector base class and so is missing the invalidation
of the iterators implied by this operation.
To fix this provide a std::erase_if overload dedicated to __gnu_debug::vector.
Doing so we can cleanup the implementation dedicated to std::vector from any
_GLIBCXX_DEBUG consideration.
libstdc++-v3/ChangeLog:
* include/debug/vector (std::erase_if, std::erase): New overloads for
std::__debug::vector instances.
* include/std/vector (std::erase_if, std::erase): Make overloads specific
to normal std::vector implementation.
* testsuite/23_containers/vector/debug/erase.cc: New test case.
* testsuite/23_containers/vector/debug/invalidation/erase.cc: New test case.
The changes needed for submdspan are:
* In submdspan related code the user-defined integer-like
types need to be copy- and move-constructable.
* The traits for writing tests that work with both left- and right,
possibly padded, layouts will also be useful for submdspan.
Therefore, this code is moved up and generalized.
* Move __offset further up in <mdspan> and fix some formatting
mistakes.
libstdc++-v3/ChangeLog:
* include/std/mdspan: Improve formatting and placement.
* testsuite/23_containers/mdspan/int_like.h: Optionally,
add move- and copy-ctors.
* testsuite/23_containers/mdspan/layouts/padded_traits.h: Move to...
* testsuite/23_containers/mdspan/layout_traits.h: ...here.
* testsuite/23_containers/mdspan/layouts/ctors.cc: Fix include.
* testsuite/23_containers/mdspan/layouts/mapping.cc: Ditto.
* testsuite/23_containers/mdspan/layouts/padded.cc: Ditto.
* testsuite/23_containers/mdspan/layouts/padded_neg.cc: Ditto.
Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com>
Signed-off-by: Luc Grosheintz <luc.grosheintz@gmail.com>
r16-5411-g5294e0a0b40674 made the "placement delete" functions noexcept,
so adjust the header synopsis test.
libstdc++-v3/ChangeLog:
* testsuite/18_support/headers/new/synopsis.cc: Add constexpr to
placement delete for C++26 and up.
This patch implements a new RTL pass that combines "li a0, 0" and
"cm.popret" into a single "cm.popretz" instruction for the Zcmp
extension.
This optimization cannot be done during prologue/epilogue expansion
because it would cause shrink-wrapping to generate incorrect code as
documented in PR113715. The dedicated RTL pass runs after shrink-wrap
but before branch shortening, safely performing this combination.
Changes since v2:
- Apply Jeff's comment
- Use CONST0_RTX rather than const0_rtx, this make this pass able to
handle (const_double:SF 0.0) as well.
- Adding test case for float/double zero return value.
Changes since v1:
- Tweak the testcase.
gcc/ChangeLog:
* config/riscv/riscv-opt-popretz.cc: New file.
* config/riscv/riscv-passes.def: Insert pass_combine_popretz before
pass_shorten_branches.
* config/riscv/riscv-protos.h (make_pass_combine_popretz): New
declaration.
* config/riscv/t-riscv: Add riscv-opt-popretz.o build rule.
* config.gcc (riscv*): Add riscv-opt-popretz.o to extra_objs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr113715.c: New test.
* gcc.target/riscv/rv32e_zcmp.c: Update expected output for
test_popretz.
* gcc.target/riscv/rv32i_zcmp.c: Likewise.
When the input of the scalar unsigned SAT_TRUNC is not Xmode,
the rtx need to zero extend to Xmode before the underlying
code gen. Most of other SAT_* code gen has leveraged
the API riscv_extend_to_xmode_reg but still have the ustrunc
missed. Then results in the failures mentioned in PR.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
PR target/122692
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_ustrunc): Leverage
riscv_extend_to_xmode_reg to take care of src rtx.
gcc/testsuite/ChangeLog:
* g++.target/riscv/pr122692-run-1.C: New test.
* g++.target/riscv/pr122692-run-2.C: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
This adds a new target hook to gimple-sel to allow targets to
do target specific massaging of the gimple IL to prepare for
expand.
Tejas will be sending up part 2 of this soon to help convert
SVE packed boolean VEC_COND_EXPR into something that we can
handle more efficiently if expanded in a different order.
We also want to use this to e.g. for Adv. SIMD prefer avoiding
!= vector compare expressions because the ISA doesn't have
this instruction and so we expand to == + ~ but changing the
expression from a MIN to MAX only for VECTOR_BOOLEAN_TYPE_P
and flipping the operands we can expand more efficient.
These are the kind of things we want to use the hook for,
not generic changes that apply to all target.
gcc/ChangeLog:
* target.def (instruction_selection): New.
* doc/tm.texi.in: Document it.
* doc/tm.texi: Regenerate
* gimple-isel.cc (pass_gimple_isel::execute): Use it.
* targhooks.cc (default_instruction_selection): New.
* targhooks.h (default_instruction_selection): New.
The inclusion of this early return statement has been discussed before,
it was ultimately left out of the original patch, but it turns out to be
necessary.
When a callback edge is being created, it is first created by
symbol_table::create_edge, which is where it is added to the call site
hash. However, its callback flag is not set at that point, so the early
return for callback edges doesn't affect it. This causes the wrong edge
to be hashed, ultimately leading to segfaults and ICEs. This happens
many times in the testsuite, the one I noticed first was
libgomp.fortran/simd7.f90.
gcc/ChangeLog:
PR ipa/122358
* cgraph.cc (cgraph_add_edge_to_call_site_hash): Add an early
return when the hashed edge is a callback-carrying edge.
Signed-off-by: Josef Melcr <josef.melcr@suse.com>
The old usage lead to makeinfo emitting text like "pseudo registers This
is the most common case. Most subregs have pseudo regs as their first
operand." when, clearly, "pseudo registers" was intended to be the name
of an item, and the rest of the paragraph a description. This is
because @itemize was used, which does not support "naming" items.
Now, the paragraph used as an example above looks like this:
pseudo registers
This is the most common case. Most ‘subreg’s have pseudo
‘reg’s as their first operand.
gcc/ChangeLog:
* doc/rtl.texi (Regs and Memory): Use @table instead of @itemize
for lists with named items.
When a major version program suffix is specified, along with
--with-gcc-major-version-only, GCC tries to install $TRIPLE-gcc-tmp into
the destination BINDIR and link it to TRIPLE-gcc-SUFFIX. However this
executable is installed in the previous step, thus leaving the gcc-tmp
unmodified.
This is because when --program-suffix=15 (any major version) and
--with-gcc-major-version-only, $(version) will be the major version
number, thus making FULL_DRIVER_NAME and GCC_TARGET_INSTALL_NAME
identical to each other. We check if these two is identical and skip the
latter step if they are.
gcc/
PR bootstrap/105664
* Makefile.in (install-driver): detect name collision when
installing the driver program.
Signed-off-by: Xinhui Yang <cyan@cyano.uk>
We currently have two ways to distinguish GNU and non-GNU assemblers and
linkers:
* USE_GAS and USE_GLD, defined via gcc/config/usegas.h and usegld.h
which are included via config.gcc
* HAVE_GNU_AS and HAVE_GNU_LD, determined from gcc/configure.ac
This is confusing and leads to weird mistakes like combining both into
an undefined USE_GNU_LD. Since both are based on the same info ($gas
resp. $gnu_ld in gcc/configure.ac), it seems best to standardise on one
of them. Since the USE_* form is almost exclusively used in
Solaris-specific contexts, it's clearer to use the HAVE_GNU_* forms
instead.
This is what this patch does.
Most of the changes are either Solaris-specific or border on obvious.
Outside of Solaris code, there are only two cases:
* gcc/config/ia64/hpux.h has one macro guarded by !USE_GAS. This wasn't
defined before since the configuration for this target doesn't include
usegas.h. However, the code is still needed, so the HAVE_GNU_AS form is
now used.
* Uses of usegas.h in various powerpc*-*-* configurations in
gcc/config.gcc. Those make no difference since USE_GAS isn't used in any
of the affected files.
Bootstrapped without regressions on i386-pc-solaris2.11 and
sparc-sun-solaris2.11 (as/ld, gas/ld, and gas/gld configurations).
2025-11-18 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
gcc:
* config/i386/sol2.h: Replace USE_GAS by HAVE_GNU_AS.
Replace USE_GLD by HAVE_GNU_LD.
* config/sol2.h: Likewise.
* config/sparc/sol2.h: Likewise.
* config/i386/i386.cc (i386_solaris_elf_named_section)
[TARGET_SOLARIS]: Replace USE_GAS by HAVE_GNU_AS.
* config/ia64/hpux.h: Likewise.
* config.gcc: Remove usegas.h, usegld.h.
* config/usegas.h: Remove.
* config/usegld.h: Remove
gcc/go:
* gospec.cc (lang_specific_driver) [TARGET_SOLARIS]: Replace
USE_GLD by HAVE_GNU_LD.
The various LINK_ARCH*_SPECs proved to be way more complex than
necessary:
* All uses of -YP,* can just go: they match the Solaris and GNU ld
defaults. In addition, the /usr/lib/libp entries are now superfluous:
they only contain compatiblity symlinks to their counterparts in
/usr/lib. The %R parts are superceded by the -z sysroot/--sysroot
options.
* With those options gone, LINK_ARCH{32,64}_SPEC_BASE are now identical
and can be merged.
* It's no longer necessary to use arch-specific versions of the Solaris
ld map.below4G linker map: with the new v2 mapfile syntax a single
file can be used for all of SPARC, and x86, 32 and 64-bit.
* Similarly, with LINK_ARCH{32,64,DEFAULT}_SPEC being identical, a
common LINK_ARCH_SPEC can be used with the single difference (erroring
out on the non-default multilib in non-multilib configurations,
e.g. -m64 for -m32-only configs) moved to a separate
LINK_ARCH_ERROR_SPEC.
Bootstrapped without regressions on {i386,amd64}-pc-solaris2.11,
sparc{,v9}-sun-solaris2.11 with as/ld, gas/ld, and gas/gld plus
--disable-multilib builds of those.
2025-11-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
gcc:
* config/sol2.h (LINK_ARCH32_SPEC_BASE): Don't provide -YP
defaults. Rename to ...
(LINK_ARCH_SPEC_BASE): ... this.
(LINK_ARCH32_SPEC): Remove.
(LINK_ARCH64_SPEC_BASE): Remove.
(LINK_ARCH64_SPEC): Rename to ...
(LINK_ARCH_SPEC_1): ... this.
[!USE_GLD]: Simplify map.below4G use.
(LINK_ARCH_ERROR_SPEC): New macro.
(LINK_ARCH32_SPEC): Remove.
(LINK_ARCH_DEFAULT_SPEC): Remove.
(LINK_ARCH_SPEC): Simplify using LINK_ARCH_ERROR_SPEC,
LINK_ARCH_SPEC_1.
(SUBTARGET_EXTRA_SPECS): Remove link_arch32, link_arch64
link_arch_default.
This function is just a boring large switch-case which can be replaced
completely with a simple RTL templete in the .md file.
gcc/
* config/loongarch/lsx.md (vec_perm<mode>): Expand directly with
RTL template.
* config/loongarch/loongarch-protos.h
(loongarch_expand_vec_perm): Delete.
* config/loongarch/loongarch.cc (loongarch_expand_vec_perm):
Delete.
De-duplicate the login by introducing gen_lasx_xvpermi_d (mode, ...)
with "@". Also remove the merge_two label: we should really not (ab)use
goto when avoiding it is trivial.
Link: https://dl.acm.org/doi/10.5555/1241515.1241518
gcc/
* config/loongarch/lasx.md (lasx_xvpermi_d): Add "@".
* config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1):
Use gen_lasx_xvpermi_d instead of
gen_lasx_xvpermi_d_{v32qi,v16hi} to deduplicate the logic. Do
structrual programming instead of goto and label.
Clamp the selector using the actual number of elements 2w instead of the
fixed value 0x1f. So we can simply compare the clamped selector and w
to generate the mask for blending.
gcc/
* config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1):
Clamp the selector using the twice of actual number of elements.
Compare the clamped selector with the element number to get the
blending mask.
Prepare to get rid of some long switch-case constructs.
gcc/
* config/loongarch/lasx.md (lasx_xvshuf_b): Remove.
(lasx_xvshuf_<lasxfmt_f): Remove.
(unspec): Remove UNSPEC_LASX_XVSHUF and UNSPEC_LASX_XVSHUF_B.
* config/loongarch/lsx.md (lsx_vshuf_b): Remove.
(lsx_vshuf_<lasxfmt_f): Remove.
(unspec): Remove UNSPEC_LSX_VSHUF and UNSPEC_LSX_VSHUF_B.
* config/loongarch/simd.md (unspec): Add UNSPEC_SIMD_VSHUF.
(@simd_vshuf): New define_insn.
(<simd_isa>_<x>vshuf_<simdfmt><_f>): New define_expand.
* config/loongarch/loongarch.cc
(loongarch_try_expand_lsx_vshuf_const): Call gen_simd_vshuf
instead of gen_lasx_xvshuf and gen_lasx_xvshuf_b.
(loongarch_expand_vec_perm_const): Likewise.
